Added bitcell as input to array, but there are DRC errors now.

compiler/modules/bank.py

@@ -401,18 +401,18 @@ class bank(design.design):
     def add_modules(self):
         """ Add all the modules using the class loader """
         
-
-        self.bitcell_array = factory.create(module_type="bitcell_array",
-                                            cols=self.num_cols,
-                                            rows=self.num_rows)
-        self.add_mod(self.bitcell_array)
-        
         # create arrays of bitline and bitline_bar names for read, write, or all ports
         self.bitcell = factory.create(module_type="bitcell") 
         self.bl_names = self.bitcell.list_all_bl_names()
         self.br_names = self.bitcell.list_all_br_names()
         self.wl_names = self.bitcell.list_all_wl_names()
         self.bitline_names = self.bitcell.list_all_bitline_names()
+        
+        self.bitcell_array = factory.create(module_type="bitcell_array",
+                                            cols=self.num_cols,
+                                            rows=self.num_rows,
+                                            bitcell=self.bitcell)
+        self.add_mod(self.bitcell_array)
 
         self.precharge_array = []
         for port in self.all_ports:

compiler/modules/bitcell_array.py

@@ -19,13 +19,14 @@ class bitcell_array(design.design):
     and word line is connected by abutment.
     Connects the word lines and bit lines.
     """
-    def __init__(self, cols, rows, name):
+    def __init__(self, cols, rows, name, bitcell):
         design.design.__init__(self, name)
         debug.info(1, "Creating {0} {1} x {2}".format(self.name, rows, cols))
         self.add_comment("rows: {0} cols: {1}".format(rows, cols))
 
         self.column_size = cols
         self.row_size = rows
+        self.cell = bitcell
 
         self.create_netlist()
         if not OPTS.netlist_only:
@@ -84,8 +85,6 @@ class bitcell_array(design.design):
 
     def add_modules(self):
         """ Add the modules used in this design """
-        self.cell = factory.create(module_type="bitcell")
-        debug.info(1,"Cell mod created, id={}".format(id(self.cell)))
         self.add_mod(self.cell)
 
     def create_instances(self):

compiler/modules/replica_bitline.py

@@ -86,10 +86,12 @@ class replica_bitline(design.design):
         self.replica_bitcell = factory.create(module_type="replica_bitcell")
         self.add_mod(self.replica_bitcell)
 
+        bitcell = factory.create(module_type="bitcell")
         # This is the replica bitline load column that is the height of our array
         self.rbl = factory.create(module_type="bitcell_array",
                                   cols=1,
-                                  rows=self.bitcell_loads)
+                                  rows=self.bitcell_loads,
+                                  bitcell=bitcell)
         self.add_mod(self.rbl)
 
         # FIXME: The FO and depth of this should be tuned