diff --git a/compiler/modules/replica_column.py b/compiler/modules/replica_column.py
index eb3116d3..c75bc9ee 100644
--- a/compiler/modules/replica_column.py
+++ b/compiler/modules/replica_column.py
@@ -188,6 +188,8 @@ class replica_column(design.design):
             for pin_name in ["vdd", "gnd"]:
                 if inst in [self.cell_inst[0], self.cell_inst[self.total_size - 1]]:
                     self.copy_power_pins(inst, pin_name)
+                else:
+                    self.copy_layout_pin(inst, pin_name)
 
     def get_bitcell_pins(self, row, col):
         """ Creates a list of connections in the bitcell,