mirror of https://github.com/VLSIDA/OpenRAM.git
Fix missing imports in replica bitcells.
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2f12c77668
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29f4ee492b
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@ -8,7 +8,8 @@
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import debug
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import bitcell_base
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from tech import cell_properties as props
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from tech import parameter
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from tech import parameter, drc
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import logical_effort
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class replica_bitcell(bitcell_base.bitcell_base):
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@ -47,7 +48,7 @@ class replica_bitcell(bitcell_base.bitcell_base):
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"""Bitcell power in nW. Only characterizes leakage."""
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from tech import spice
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leakage = spice["bitcell_leakage"]
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dynamic = 0 #temporary
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dynamic = 0 # FIXME
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total_power = self.return_power(dynamic, leakage)
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return total_power
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@ -8,7 +8,8 @@
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import debug
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import bitcell_base
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from tech import cell_properties as props
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from tech import parameter
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from tech import parameter, drc
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import logical_effort
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class replica_bitcell_1rw_1r(bitcell_base.bitcell_base):
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@ -8,6 +8,8 @@
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import debug
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import bitcell_base
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from tech import cell_properties as props
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from tech import parameter, drc
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import logical_effort
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class replica_bitcell_1w_1r(bitcell_base.bitcell_base):
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