diff --git a/compiler/bitcells/replica_bitcell.py b/compiler/bitcells/replica_bitcell.py
index 7ce9d433..74e121ee 100644
--- a/compiler/bitcells/replica_bitcell.py
+++ b/compiler/bitcells/replica_bitcell.py
@@ -8,7 +8,8 @@
 import debug
 import bitcell_base
 from tech import cell_properties as props
-from tech import parameter
+from tech import parameter, drc
+import logical_effort
 
 
 class replica_bitcell(bitcell_base.bitcell_base):
@@ -31,23 +32,23 @@ class replica_bitcell(bitcell_base.bitcell_base):
 
     def get_stage_effort(self, load):
         parasitic_delay = 1
-        size = 0.5 #This accounts for bitline being drained thought the access TX and internal node
-        cin = 3 #Assumes always a minimum sizes inverter. Could be specified in the tech.py file.
-        read_port_load = 0.5 #min size NMOS gate load
-        return logical_effort.logical_effort('bitline', size, cin, load+read_port_load, parasitic_delay, False)
+        size = 0.5 # This accounts for bitline being drained thought the access TX and internal node
+        cin = 3 # Assumes always a minimum sizes inverter. Could be specified in the tech.py file.
+        read_port_load = 0.5 # min size NMOS gate load
+        return logical_effort.logical_effort('bitline', size, cin, load + read_port_load, parasitic_delay, False)
 
     def input_load(self):
         """Return the relative capacitance of the access transistor gates"""
 
         # FIXME: This applies to bitline capacitances as well.
-        access_tx_cin = parameter["6T_access_size"]/drc["minwidth_tx"]
-        return 2*access_tx_cin
+        access_tx_cin = parameter["6T_access_size"] / drc["minwidth_tx"]
+        return 2 * access_tx_cin
 
     def analytical_power(self, corner, load):
         """Bitcell power in nW. Only characterizes leakage."""
         from tech import spice
         leakage = spice["bitcell_leakage"]
-        dynamic = 0 #temporary
+        dynamic = 0 # FIXME
         total_power = self.return_power(dynamic, leakage)
         return total_power
 
diff --git a/compiler/bitcells/replica_bitcell_1rw_1r.py b/compiler/bitcells/replica_bitcell_1rw_1r.py
index 60e160c3..9dc9aac9 100644
--- a/compiler/bitcells/replica_bitcell_1rw_1r.py
+++ b/compiler/bitcells/replica_bitcell_1rw_1r.py
@@ -8,7 +8,8 @@
 import debug
 import bitcell_base
 from tech import cell_properties as props
-from tech import parameter
+from tech import parameter, drc
+import logical_effort
 
 
 class replica_bitcell_1rw_1r(bitcell_base.bitcell_base):
@@ -34,25 +35,25 @@ class replica_bitcell_1rw_1r(bitcell_base.bitcell_base):
 
     def get_stage_effort(self, load):
         parasitic_delay = 1
-        size = 0.5 #This accounts for bitline being drained thought the access TX and internal node
-        cin = 3 #Assumes always a minimum sizes inverter. Could be specified in the tech.py file.
-        read_port_load = 0.5 #min size NMOS gate load
-        return logical_effort.logical_effort('bitline', size, cin, load+read_port_load, parasitic_delay, False)
+        size = 0.5 # This accounts for bitline being drained thought the access TX and internal node
+        cin = 3 # Assumes always a minimum sizes inverter. Could be specified in the tech.py file.
+        read_port_load = 0.5 # min size NMOS gate load
+        return logical_effort.logical_effort('bitline', size, cin, load + read_port_load, parasitic_delay, False)
 
     def input_load(self):
         """Return the relative capacitance of the access transistor gates"""
 
         # FIXME: This applies to bitline capacitances as well.
         # FIXME: sizing is not accurate with the handmade cell. Change once cell widths are fixed.
-        access_tx_cin = parameter["6T_access_size"]/drc["minwidth_tx"]
-        return 2*access_tx_cin
+        access_tx_cin = parameter["6T_access_size"] / drc["minwidth_tx"]
+        return 2 * access_tx_cin
 
     def build_graph(self, graph, inst_name, port_nets):
         """Adds edges to graph. Multiport bitcell timing graph is too complex
            to use the add_graph_edges function."""
-        pin_dict = {pin:port for pin,port in zip(self.pins, port_nets)}
+        pin_dict = {pin: port for pin, port in zip(self.pins, port_nets)}
         pins = props.bitcell.cell_1rw1r.pin
-        #Edges hardcoded here. Essentially wl->bl/br for both ports.
+        # Edges hardcoded here. Essentially wl->bl/br for both ports.
         # Port 0 edges
         graph.add_edge(pin_dict[pins.wl0], pin_dict[pins.bl0], self)
         graph.add_edge(pin_dict[pins.wl0], pin_dict[pins.br0], self)
diff --git a/compiler/bitcells/replica_bitcell_1w_1r.py b/compiler/bitcells/replica_bitcell_1w_1r.py
index 4f09ed4f..59fa4676 100644
--- a/compiler/bitcells/replica_bitcell_1w_1r.py
+++ b/compiler/bitcells/replica_bitcell_1w_1r.py
@@ -8,6 +8,8 @@
 import debug
 import bitcell_base
 from tech import cell_properties as props
+from tech import parameter, drc
+import logical_effort
 
 
 class replica_bitcell_1w_1r(bitcell_base.bitcell_base):
@@ -33,26 +35,26 @@ class replica_bitcell_1w_1r(bitcell_base.bitcell_base):
 
     def get_stage_effort(self, load):
         parasitic_delay = 1
-        size = 0.5 #This accounts for bitline being drained thought the access TX and internal node
-        cin = 3 #Assumes always a minimum sizes inverter. Could be specified in the tech.py file.
-        read_port_load = 0.5 #min size NMOS gate load
-        return logical_effort.logical_effort('bitline', size, cin, load+read_port_load, parasitic_delay, False)
+        size = 0.5 # This accounts for bitline being drained thought the access TX and internal node
+        cin = 3 # Assumes always a minimum sizes inverter. Could be specified in the tech.py file.
+        read_port_load = 0.5 # min size NMOS gate load
+        return logical_effort.logical_effort('bitline', size, cin, load + read_port_load, parasitic_delay, False)
 
     def input_load(self):
         """Return the relative capacitance of the access transistor gates"""
 
         # FIXME: This applies to bitline capacitances as well.
         # FIXME: sizing is not accurate with the handmade cell. Change once cell widths are fixed.
-        access_tx_cin = parameter["6T_access_size"]/drc["minwidth_tx"]
-        return 2*access_tx_cin
+        access_tx_cin = parameter["6T_access_size"] / drc["minwidth_tx"]
+        return 2 * access_tx_cin
 
     def build_graph(self, graph, inst_name, port_nets):
         """Adds edges to graph. Multiport bitcell timing graph is too complex
            to use the add_graph_edges function."""
-        debug.info(1,'Adding edges for {}'.format(inst_name))
-        pin_dict = {pin:port for pin,port in zip(self.pins, port_nets)}
+        debug.info(1, 'Adding edges for {}'.format(inst_name))
+        pin_dict = {pin: port for pin, port in zip(self.pins, port_nets)}
         pins = props.bitcell.cell_1w1r.pin
-        #Edges hardcoded here. Essentially wl->bl/br for the read port.
+        # Edges hardcoded here. Essentially wl->bl/br for the read port.
         # Port 1 edges
         graph.add_edge(pin_dict[pins.wl1], pin_dict[pins.bl1], self)
         graph.add_edge(pin_dict[pins.wl1], pin_dict[pins.br1], self)