Don't force check in lib characterization. PEP8 formatting.

compiler/base/hierarchy_design.py

@@ -52,7 +52,7 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout):
         if not force_check and not OPTS.check_lvsdrc:
             return ("skipped", "skipped")
         # Do not run if disabled in options.
-        if (OPTS.inline_lvsdrc or force_check):
+        if (OPTS.inline_lvsdrc or force_check or final_verification):
 
             tempspice = "{0}/{1}.sp".format(OPTS.openram_temp, self.name)
             tempgds = "{0}/{1}.gds".format(OPTS.openram_temp, self.name)
@@ -61,6 +61,10 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout):
             # Final verification option does not allow nets to be connected by label.
             num_drc_errors = verify.run_drc(self.name, tempgds, extract=True, final_verification=final_verification)
             num_lvs_errors = verify.run_lvs(self.name, tempgds, tempspice, final_verification=final_verification)
+
+            # force_check is used to determine decoder height and other things, so we shouldn't fail
+            # if that flag is set
+            if OPTS.inline_lvsdrc and not force_check:
                 debug.check(num_drc_errors == 0,
                             "DRC failed for {0} with {1} error(s)".format(self.name,
                                                                           num_drc_errors))

compiler/characterizer/lib.py

@@ -621,7 +621,7 @@ class lib:
                         ))
 
         # information of checks
-        (drc_errors, lvs_errors) = self.sram.DRC_LVS(final_verification=True, force_check=True)
+        (drc_errors, lvs_errors) = self.sram.DRC_LVS(final_verification=True)
         datasheet.write("{0},{1},".format(drc_errors, lvs_errors))
         
         # write area

compiler/modules/hierarchical_decoder.py

@@ -36,9 +36,10 @@ class hierarchical_decoder(design.design):
 
     def find_decoder_height(self):
         b = factory.create(module_type="bitcell")
-
+        # Old behavior
         return (b.height, 1)
 
+        # Search for the smallest multiple that works
         cell_multiple = 1
         while cell_multiple < 3:
             cell_height = cell_multiple * b.height

compiler/sram/sram_base.py

@@ -121,7 +121,7 @@ class sram_base(design, verilog, lef):
 
         start_time = datetime.datetime.now()
         # We only enable final verification if we have routed the design
-        self.DRC_LVS(final_verification=OPTS.route_supplies, force_check=True)
+        self.DRC_LVS(final_verification=OPTS.route_supplies)
         if not OPTS.is_unit_test:
             print_time("Verification", datetime.datetime.now(), start_time)
 

compiler/verify/none.py

@@ -16,6 +16,7 @@ drc_warned = False
 lvs_warned = False
 pex_warned = False
 
+
 def run_drc(cell_name, gds_name, extract=False, final_verification=False):
     global drc_warned
     if not drc_warned:
@@ -24,6 +25,7 @@ def run_drc(cell_name, gds_name, extract=False, final_verification=False):
     # Since we warned, return a failing test.
     return 1
 
+
 def run_lvs(cell_name, gds_name, sp_name, final_verification=False):
     global lvs_warned
     if not lvs_warned:
@@ -32,6 +34,7 @@ def run_lvs(cell_name, gds_name, sp_name, final_verification=False):
     # Since we warned, return a failing test.
     return 1
 
+
 def run_pex(name, gds_name, sp_name, output=None, final_verification=False):
     global pex_warned
     if not pex_warned:
@@ -40,9 +43,14 @@ def run_pex(name, gds_name, sp_name, output=None, final_verification=False):
     # Since we warned, return a failing test.
     return 1
 
+
 def print_drc_stats():
     pass
+
+
 def print_lvs_stats():
     pass
+
+
 def print_pex_stats():
     pass