Fix name of column mux.

This commit is contained in:
Matt Guthaus 2018-02-02 14:26:39 -08:00
parent 9d7dc4c552
commit 27dbb95c19
2 changed files with 6 additions and 4 deletions

View File

@ -12,9 +12,10 @@ class single_level_column_mux(design.design):
Creates a single columnmux cell. Creates a single columnmux cell.
""" """
def __init__(self, name, tx_size): def __init__(self, tx_size):
name="single_level_column_mux_{}".format(tx_size)
design.design.__init__(self, name) design.design.__init__(self, name)
debug.info(2, "create single columnmux cell: {0}".format(name)) debug.info(2, "create single column mux cell: {0}".format(name))
c = reload(__import__(OPTS.bitcell)) c = reload(__import__(OPTS.bitcell))
self.mod_bitcell = getattr(c, OPTS.bitcell) self.mod_bitcell = getattr(c, OPTS.bitcell)

View File

@ -43,8 +43,8 @@ class single_level_column_mux_array(design.design):
self.add_enclosure(self.mux_inst, "pwell") self.add_enclosure(self.mux_inst, "pwell")
def add_modules(self): def add_modules(self):
self.mux = single_level_column_mux(name="single_level_column_mux", # FIXME: Why is this 8x?
tx_size=8) self.mux = single_level_column_mux(tx_size=8)
self.add_mod(self.mux) self.add_mod(self.mux)
@ -58,6 +58,7 @@ class single_level_column_mux_array(design.design):
# one set of metal1 routes for select signals and a pair to interconnect the mux outputs bl/br # one set of metal1 routes for select signals and a pair to interconnect the mux outputs bl/br
# one extra route pitch is to space from the sense amp # one extra route pitch is to space from the sense amp
self.route_height = (self.words_per_row + 3)*self.m1_pitch self.route_height = (self.words_per_row + 3)*self.m1_pitch
# mux height plus routing signal height plus well spacing at the top # mux height plus routing signal height plus well spacing at the top
self.height = self.mux.height + self.route_height + drc["pwell_to_nwell"] self.height = self.mux.height + self.route_height + drc["pwell_to_nwell"]