mirror of https://github.com/VLSIDA/OpenRAM.git
Fix name of column mux.
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9d7dc4c552
commit
27dbb95c19
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@ -12,9 +12,10 @@ class single_level_column_mux(design.design):
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Creates a single columnmux cell.
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Creates a single columnmux cell.
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"""
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"""
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def __init__(self, name, tx_size):
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def __init__(self, tx_size):
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name="single_level_column_mux_{}".format(tx_size)
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design.design.__init__(self, name)
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design.design.__init__(self, name)
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debug.info(2, "create single columnmux cell: {0}".format(name))
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debug.info(2, "create single column mux cell: {0}".format(name))
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c = reload(__import__(OPTS.bitcell))
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c = reload(__import__(OPTS.bitcell))
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self.mod_bitcell = getattr(c, OPTS.bitcell)
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self.mod_bitcell = getattr(c, OPTS.bitcell)
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@ -43,8 +43,8 @@ class single_level_column_mux_array(design.design):
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self.add_enclosure(self.mux_inst, "pwell")
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self.add_enclosure(self.mux_inst, "pwell")
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def add_modules(self):
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def add_modules(self):
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self.mux = single_level_column_mux(name="single_level_column_mux",
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# FIXME: Why is this 8x?
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tx_size=8)
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self.mux = single_level_column_mux(tx_size=8)
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self.add_mod(self.mux)
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self.add_mod(self.mux)
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@ -58,6 +58,7 @@ class single_level_column_mux_array(design.design):
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# one set of metal1 routes for select signals and a pair to interconnect the mux outputs bl/br
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# one set of metal1 routes for select signals and a pair to interconnect the mux outputs bl/br
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# one extra route pitch is to space from the sense amp
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# one extra route pitch is to space from the sense amp
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self.route_height = (self.words_per_row + 3)*self.m1_pitch
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self.route_height = (self.words_per_row + 3)*self.m1_pitch
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# mux height plus routing signal height plus well spacing at the top
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# mux height plus routing signal height plus well spacing at the top
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self.height = self.mux.height + self.route_height + drc["pwell_to_nwell"]
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self.height = self.mux.height + self.route_height + drc["pwell_to_nwell"]
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