From 27dbb95c19e99d5e826b8e3d0e517a356e52e65a Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Fri, 2 Feb 2018 14:26:39 -0800 Subject: [PATCH] Fix name of column mux. --- compiler/single_level_column_mux.py | 5 +++-- compiler/single_level_column_mux_array.py | 5 +++-- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/compiler/single_level_column_mux.py b/compiler/single_level_column_mux.py index 373aaee0..3358190e 100644 --- a/compiler/single_level_column_mux.py +++ b/compiler/single_level_column_mux.py @@ -12,9 +12,10 @@ class single_level_column_mux(design.design): Creates a single columnmux cell. """ - def __init__(self, name, tx_size): + def __init__(self, tx_size): + name="single_level_column_mux_{}".format(tx_size) design.design.__init__(self, name) - debug.info(2, "create single columnmux cell: {0}".format(name)) + debug.info(2, "create single column mux cell: {0}".format(name)) c = reload(__import__(OPTS.bitcell)) self.mod_bitcell = getattr(c, OPTS.bitcell) diff --git a/compiler/single_level_column_mux_array.py b/compiler/single_level_column_mux_array.py index 0e2c8752..fcdbcbc4 100644 --- a/compiler/single_level_column_mux_array.py +++ b/compiler/single_level_column_mux_array.py @@ -43,8 +43,8 @@ class single_level_column_mux_array(design.design): self.add_enclosure(self.mux_inst, "pwell") def add_modules(self): - self.mux = single_level_column_mux(name="single_level_column_mux", - tx_size=8) + # FIXME: Why is this 8x? + self.mux = single_level_column_mux(tx_size=8) self.add_mod(self.mux) @@ -58,6 +58,7 @@ class single_level_column_mux_array(design.design): # one set of metal1 routes for select signals and a pair to interconnect the mux outputs bl/br # one extra route pitch is to space from the sense amp self.route_height = (self.words_per_row + 3)*self.m1_pitch + # mux height plus routing signal height plus well spacing at the top self.height = self.mux.height + self.route_height + drc["pwell_to_nwell"]