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fix custom bitcell labeling; fix gds scaling in labeling
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+5
-5
@@ -4,15 +4,15 @@
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* SPICE3 file created from cell_6t.ext - technology: scmos
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* Inverter 1
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M1000 Q Qbar vdd vdd p w=0.6u l=0.8u
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M1002 Q Qbar gnd gnd n w=1.6u l=0.4u
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M1000 Q Q_bar vdd vdd p w=0.6u l=0.8u
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M1002 Q Q_bar gnd gnd n w=1.6u l=0.4u
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* Inverter 2
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M1001 vdd Q Qbar vdd p w=0.6u l=0.8u
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M1003 gnd Q Qbar gnd n w=1.6u l=0.4u
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M1001 vdd Q Q_bar vdd p w=0.6u l=0.8u
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M1003 gnd Q Q_bar gnd n w=1.6u l=0.4u
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* Access transistors
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M1004 Q wl bl gnd n w=0.8u l=0.4u
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M1005 Qbar wl br gnd n w=0.8u l=0.4u
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M1005 Q_bar wl br gnd n w=0.8u l=0.4u
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.ENDS
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+5
-5
@@ -3,15 +3,15 @@
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.SUBCKT dummy_cell_6t bl br wl vdd gnd
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* Inverter 1
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M1000 Q Qbar vdd vdd p w=0.6u l=0.8u
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M1002 Q Qbar gnd gnd n w=1.6u l=0.4u
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M1000 Q Q_bar vdd vdd p w=0.6u l=0.8u
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M1002 Q Q_bar gnd gnd n w=1.6u l=0.4u
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* Inverter 2
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M1001 vdd Q Qbar vdd p w=0.6u l=0.8u
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M1003 gnd Q Qbar gnd n w=1.6u l=0.4u
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M1001 vdd Q Q_bar vdd p w=0.6u l=0.8u
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M1003 gnd Q Q_bar gnd n w=1.6u l=0.4u
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* Access transistors
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M1004 Q wl bl_noconn gnd n w=0.8u l=0.4u
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M1005 Qbar wl br_noconn gnd n w=0.8u l=0.4u
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M1005 Q_bar wl br_noconn gnd n w=0.8u l=0.4u
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.ENDS
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