From 2733c3bf3fe2acd23b6d89f9a8e7ca2c27b8e326 Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Wed, 15 Jan 2020 09:00:02 +0000 Subject: [PATCH] fix custom bitcell labeling; fix gds scaling in labeling --- compiler/base/geometry.py | 11 ++++---- compiler/bitcells/bitcell.py | 4 +-- compiler/bitcells/bitcell_base.py | 25 ++++++++++++------- technology/scn4m_subm/sp_lib/cell_6t.sp | 10 ++++---- technology/scn4m_subm/sp_lib/dummy_cell_6t.sp | 10 ++++---- 5 files changed, 34 insertions(+), 26 deletions(-) diff --git a/compiler/base/geometry.py b/compiler/base/geometry.py index 46a7bd6e..885b139a 100644 --- a/compiler/base/geometry.py +++ b/compiler/base/geometry.py @@ -267,14 +267,15 @@ class instance(geometry): path.append(node) if node.mod.name == cell_name: - print("bitcell found") cell_paths.append(copy.copy(path)) + + normalized_storage_nets = node.mod.get_normalized_storage_nets_offset() - Q_x = node.mod.get_normalized_storage_net_offset()[0][0] - Q_y = node.mod.get_normalized_storage_net_offset()[0][1] + Q_x = normalized_storage_nets[0][0] + Q_y = normalized_storage_nets[0][1] - Q_bar_x = node.mod.get_normalized_storage_net_offset()[1][0] - Q_bar_y = node.mod.get_normalized_storage_net_offset()[1][1] + Q_bar_x = normalized_storage_nets[1][0] + Q_bar_y = normalized_storage_nets[1][1] if node.mirror == 'MX': Q_y = -1 * Q_y diff --git a/compiler/bitcells/bitcell.py b/compiler/bitcells/bitcell.py index b22c9a46..52552413 100644 --- a/compiler/bitcells/bitcell.py +++ b/compiler/bitcells/bitcell.py @@ -18,9 +18,9 @@ class bitcell(bitcell_base.bitcell_base): the layout and netlist should be available in the technology library. """ - + pin_names = ["bl", "br", "wl", "vdd", "gnd"] - storage_nets = ['Q', 'Qbar'] + storage_nets = ['Q', 'Q_bar'] type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"] (width, height) = utils.get_libcell_size("cell_6t", GDS["unit"], diff --git a/compiler/bitcells/bitcell_base.py b/compiler/bitcells/bitcell_base.py index 62bcf1bb..0a5624bd 100644 --- a/compiler/bitcells/bitcell_base.py +++ b/compiler/bitcells/bitcell_base.py @@ -88,27 +88,34 @@ class bitcell_base(design.design): # If we generated the bitcell, we already know where Q and Q_bar are if OPTS.bitcell is not "pbitcell": self.storage_net_offsets = [] - for i in range(0, len(self.get_storage_net_names())): + for i in range(len(self.get_storage_net_names())): for text in self.gds.getTexts(layer["metal1"]): if self.storage_nets[i] == text.textString.rstrip('\x00'): - print(text.textString + "sucess") + self.storage_net_offsets.append(text.coordinates[0]) + for i in range(len(self.storage_net_offsets)): + self.storage_net_offsets[i] = tuple([self.gds.info["units"][0] * x for x in self.storage_net_offsets[i]]) + return(self.storage_net_offsets) - def get_normalized_storage_net_offset(self): + def get_normalized_storage_nets_offset(self): """ Convert storage net offset to be relative to the bottom left corner of the bitcell. This is useful for making sense of offsets outside of the bitcell. """ - print("get normalized") - Q_x = self.get_storage_net_offset()[0][0] - self.leftmost_xpos - Q_y = self.get_storage_net_offset()[0][1] - self.botmost_ypos - Q_bar_x = self.get_storage_net_offset()[1][0] - self.leftmost_xpos - Q_bar_y = self.get_storage_net_offset()[1][1] - self.botmost_ypos + if OPTS.bitcell is not "pbitcell": + normalized_storage_net_offset = self.get_storage_net_offset() - normalized_storage_net_offset = [[Q_x,Q_y],[Q_bar_x,Q_bar_y]] + else: + net_offset = self.get_storage_net_offset() + Q_x = net_offset[0][0] - self.leftmost_xpos + Q_y = net_offset[0][1] - self.botmost_ypos + Q_bar_x = net_offset[1][0] - self.leftmost_xpos + Q_bar_y = net_offset[1][1] - self.botmost_ypos + + normalized_storage_net_offset = [[Q_x,Q_y],[Q_bar_x,Q_bar_y]] return normalized_storage_net_offset diff --git a/technology/scn4m_subm/sp_lib/cell_6t.sp b/technology/scn4m_subm/sp_lib/cell_6t.sp index bb430893..dc724007 100644 --- a/technology/scn4m_subm/sp_lib/cell_6t.sp +++ b/technology/scn4m_subm/sp_lib/cell_6t.sp @@ -4,15 +4,15 @@ * SPICE3 file created from cell_6t.ext - technology: scmos * Inverter 1 -M1000 Q Qbar vdd vdd p w=0.6u l=0.8u -M1002 Q Qbar gnd gnd n w=1.6u l=0.4u +M1000 Q Q_bar vdd vdd p w=0.6u l=0.8u +M1002 Q Q_bar gnd gnd n w=1.6u l=0.4u * Inverter 2 -M1001 vdd Q Qbar vdd p w=0.6u l=0.8u -M1003 gnd Q Qbar gnd n w=1.6u l=0.4u +M1001 vdd Q Q_bar vdd p w=0.6u l=0.8u +M1003 gnd Q Q_bar gnd n w=1.6u l=0.4u * Access transistors M1004 Q wl bl gnd n w=0.8u l=0.4u -M1005 Qbar wl br gnd n w=0.8u l=0.4u +M1005 Q_bar wl br gnd n w=0.8u l=0.4u .ENDS diff --git a/technology/scn4m_subm/sp_lib/dummy_cell_6t.sp b/technology/scn4m_subm/sp_lib/dummy_cell_6t.sp index 3b0584df..c5b6ff9d 100644 --- a/technology/scn4m_subm/sp_lib/dummy_cell_6t.sp +++ b/technology/scn4m_subm/sp_lib/dummy_cell_6t.sp @@ -3,15 +3,15 @@ .SUBCKT dummy_cell_6t bl br wl vdd gnd * Inverter 1 -M1000 Q Qbar vdd vdd p w=0.6u l=0.8u -M1002 Q Qbar gnd gnd n w=1.6u l=0.4u +M1000 Q Q_bar vdd vdd p w=0.6u l=0.8u +M1002 Q Q_bar gnd gnd n w=1.6u l=0.4u * Inverter 2 -M1001 vdd Q Qbar vdd p w=0.6u l=0.8u -M1003 gnd Q Qbar gnd n w=1.6u l=0.4u +M1001 vdd Q Q_bar vdd p w=0.6u l=0.8u +M1003 gnd Q Q_bar gnd n w=1.6u l=0.4u * Access transistors M1004 Q wl bl_noconn gnd n w=0.8u l=0.4u -M1005 Qbar wl br_noconn gnd n w=0.8u l=0.4u +M1005 Q_bar wl br_noconn gnd n w=0.8u l=0.4u .ENDS