Further fixes for new verilog naming convention

compiler/modules/sram.py

@@ -57,13 +57,11 @@ class sram():
         self.s.gds_write(name)
 
     def verilog_write(self, name):
+        self.s.verilog_write(name)
         if self.num_banks != 1:
-            self.s.verilog_write(name)
             from .sram_multibank import sram_multibank
             mb = sram_multibank(self.s)
             mb.verilog_write(name[:-2] + '_top.v')
-        else:
-            self.s.verilog_write(name)
 
     def extended_config_write(self, name):
         """Dump config file with all options.

compiler/modules/sram_multibank.py

@@ -12,8 +12,8 @@ class sram_multibank:
         r_ports = [i for i in sram.all_ports if i in sram.read_ports and i not in sram.write_ports]
         w_ports = [i for i in sram.all_ports if i not in sram.read_ports and i in sram.write_ports]
         self.dict = {
-            'module_name': OPTS.output_name,
-            'bank_module_name': OPTS.output_name + '_1bank',
+            'module_name': sram.name + '_top',
+            'bank_module_name': sram.name,
             'vdd': 'vdd',
             'gnd': 'gnd',
             'ports': sram.all_ports,
@@ -34,7 +34,7 @@ class sram_multibank:
         t.write(name)
         with open(name, 'r') as f:
             text = f.read()
-            badComma = re.compile(',(\s*\n\s*\);)')
+            badComma = re.compile(r',(\s*\n\s*\);)')
             text = badComma.sub(r'\1', text)
         with open(name, 'w') as f:
             f.write(text)