From 25cc08db80f0da15862440245c380e7ace4f122d Mon Sep 17 00:00:00 2001 From: Bugra Onal Date: Thu, 18 Aug 2022 11:03:13 -0700 Subject: [PATCH] Further fixes for new verilog naming convention --- compiler/base/verilog.py | 2 +- compiler/modules/sram.py | 4 +- compiler/modules/sram_multibank.py | 6 +- compiler/tests/25_verilog_multibank_test.py | 6 +- .../tests/golden/sram_2_16_2_scn4m_subm.v | 138 +++++++----------- .../golden/sram_2_16_2_scn4m_subm_1bank.v | 73 --------- .../tests/golden/sram_2_16_2_scn4m_subm_top.v | 105 +++++++++++++ 7 files changed, 166 insertions(+), 168 deletions(-) delete mode 100644 compiler/tests/golden/sram_2_16_2_scn4m_subm_1bank.v create mode 100644 compiler/tests/golden/sram_2_16_2_scn4m_subm_top.v diff --git a/compiler/base/verilog.py b/compiler/base/verilog.py index 2d5a069f..b93b52e9 100644 --- a/compiler/base/verilog.py +++ b/compiler/base/verilog.py @@ -39,7 +39,7 @@ class verilog: self.gnd_name = "gnd" if self.num_banks > 1: - self.vf.write("module {0}(\n".format(self.name + '_1bank')) + self.vf.write("module {0}(\n".format(self.name)) else: self.vf.write("module {0}(\n".format(self.name)) self.vf.write("`ifdef USE_POWER_PINS\n") diff --git a/compiler/modules/sram.py b/compiler/modules/sram.py index 52a54688..6c26e5ec 100644 --- a/compiler/modules/sram.py +++ b/compiler/modules/sram.py @@ -57,13 +57,11 @@ class sram(): self.s.gds_write(name) def verilog_write(self, name): + self.s.verilog_write(name) if self.num_banks != 1: - self.s.verilog_write(name) from .sram_multibank import sram_multibank mb = sram_multibank(self.s) mb.verilog_write(name[:-2] + '_top.v') - else: - self.s.verilog_write(name) def extended_config_write(self, name): """Dump config file with all options. diff --git a/compiler/modules/sram_multibank.py b/compiler/modules/sram_multibank.py index 087f9e9d..675e0c02 100644 --- a/compiler/modules/sram_multibank.py +++ b/compiler/modules/sram_multibank.py @@ -12,8 +12,8 @@ class sram_multibank: r_ports = [i for i in sram.all_ports if i in sram.read_ports and i not in sram.write_ports] w_ports = [i for i in sram.all_ports if i not in sram.read_ports and i in sram.write_ports] self.dict = { - 'module_name': OPTS.output_name, - 'bank_module_name': OPTS.output_name + '_1bank', + 'module_name': sram.name + '_top', + 'bank_module_name': sram.name, 'vdd': 'vdd', 'gnd': 'gnd', 'ports': sram.all_ports, @@ -34,7 +34,7 @@ class sram_multibank: t.write(name) with open(name, 'r') as f: text = f.read() - badComma = re.compile(',(\s*\n\s*\);)') + badComma = re.compile(r',(\s*\n\s*\);)') text = badComma.sub(r'\1', text) with open(name, 'w') as f: f.write(text) diff --git a/compiler/tests/25_verilog_multibank_test.py b/compiler/tests/25_verilog_multibank_test.py index 72449868..91fb04ae 100755 --- a/compiler/tests/25_verilog_multibank_test.py +++ b/compiler/tests/25_verilog_multibank_test.py @@ -35,13 +35,13 @@ class multibank_verilog_test(openram_test): # it will just replaece the top-level module of the same name s = sram(c, "sram_2_16_2_{0}".format(OPTS.tech_name)) - vfile = s.name + ".v" + vfile = s.name + "_top.v" vname = OPTS.openram_temp + vfile - v1bfile = s.name + "_1bank.v" + v1bfile = s.name + ".v" v1bname = OPTS.openram_temp + v1bfile - s.verilog_write(vname) + s.verilog_write(v1bname) # let's diff the result with a golden model multi_golden = "{0}/golden/{1}".format(os.path.dirname(os.path.realpath(__file__)), vfile) diff --git a/compiler/tests/golden/sram_2_16_2_scn4m_subm.v b/compiler/tests/golden/sram_2_16_2_scn4m_subm.v index fe23faaf..93f818cd 100644 --- a/compiler/tests/golden/sram_2_16_2_scn4m_subm.v +++ b/compiler/tests/golden/sram_2_16_2_scn4m_subm.v @@ -1,105 +1,73 @@ +// OpenRAM SRAM model +// Words: 16 +// Word size: 2 -module sram ( +module sram_2_16_2_scn4m_subm( `ifdef USE_POWER_PINS vdd, gnd, `endif - clk0, - addr0, - din0, - csb0, - web0, - dout0 +// Port 0: RW + clk0,csb0,web0,addr0,din0,dout0 ); - parameter DATA_WIDTH = 2; - parameter ADDR_WIDTH= 4; - - parameter BANK_SEL = 1; - parameter NUM_WMASK = 0; + parameter DATA_WIDTH = 2 ; + parameter ADDR_WIDTH = 3 ; + parameter RAM_DEPTH = 1 << ADDR_WIDTH; + // FIXME: This delay is arbitrary. + parameter DELAY = 3 ; + parameter VERBOSE = 1 ; //Set to 0 to only display warnings + parameter T_HOLD = 1 ; //Delay to hold dout value after posedge. Value is arbitrary `ifdef USE_POWER_PINS - inout vdd; - inout gnd; + inout vdd; + inout gnd; `endif - input clk0; - input [ADDR_WIDTH - 1 : 0] addr0; - input [DATA_WIDTH - 1: 0] din0; - input csb0; - input web0; - output reg [DATA_WIDTH - 1 : 0] dout0; + input clk0; // clock + input csb0; // active low chip select + input web0; // active low write control + input [ADDR_WIDTH-1:0] addr0; + input [DATA_WIDTH-1:0] din0; + output [DATA_WIDTH-1:0] dout0; - reg [BANK_SEL - 1 : 0] addr0_reg; + reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1]; - wire [DATA_WIDTH - 1 : 0] dout0_bank0; + reg csb0_reg; + reg web0_reg; + reg [ADDR_WIDTH-1:0] addr0_reg; + reg [DATA_WIDTH-1:0] din0_reg; + reg [DATA_WIDTH-1:0] dout0; - reg web0_bank0; - - reg csb0_bank0; - - wire [DATA_WIDTH - 1 : 0] dout0_bank1; - - reg web0_bank1; - - reg csb0_bank1; - - - sram_1bank bank0 ( -`ifdef USE_POWER_PINS - .vdd(vdd), - .gnd(gnd), -`endif - .clk0(clk0), - .addr0(addr0[ADDR_WIDTH - BANK_SEL - 1 : 0]), - .din0(din0), - .csb0(csb0_bank0), - .web0(web0_bank0), - .dout0(dout0_bank0) - ); - sram_1bank bank1 ( -`ifdef USE_POWER_PINS - .vdd(vdd), - .gnd(gnd), -`endif - .clk0(clk0), - .addr0(addr0[ADDR_WIDTH - BANK_SEL - 1 : 0]), - .din0(din0), - .csb0(csb0_bank1), - .web0(web0_bank1), - .dout0(dout0_bank1) - ); - - always @(posedge clk0) begin - addr0_reg <= addr0[ADDR_WIDTH - 1 : ADDR_WIDTH - BANK_SEL]; + // All inputs are registers + always @(posedge clk0) + begin + csb0_reg = csb0; + web0_reg = web0; + addr0_reg = addr0; + din0_reg = din0; + #(T_HOLD) dout0 = 2'bx; + if ( !csb0_reg && web0_reg && VERBOSE ) + $display($time," Reading %m addr0=%b dout0=%b",addr0_reg,mem[addr0_reg]); + if ( !csb0_reg && !web0_reg && VERBOSE ) + $display($time," Writing %m addr0=%b din0=%b",addr0_reg,din0_reg); end - always @(*) begin - case (addr0_reg) - 0: begin - dout0 = dout0_bank0; - end - 1: begin - dout0 = dout0_bank1; - end - endcase + + // Memory Write Block Port 0 + // Write Operation : When web0 = 0, csb0 = 0 + always @ (negedge clk0) + begin : MEM_WRITE0 + if ( !csb0_reg && !web0_reg ) begin + mem[addr0_reg][1:0] = din0_reg[1:0]; + end end - always @(*) begin - csb0_bank0 = 1'b1; - web0_bank0 = 1'b1; - csb0_bank1 = 1'b1; - web0_bank1 = 1'b1; - case (addr0[ADDR_WIDTH - 1 : ADDR_WIDTH - BANK_SEL]) - 0: begin - web0_bank0 = web0; - csb0_bank0 = csb0; - end - 1: begin - web0_bank1 = web0; - csb0_bank1 = csb0; - end - endcase + // Memory Read Block Port 0 + // Read Operation : When web0 = 1, csb0 = 0 + always @ (negedge clk0) + begin : MEM_READ0 + if (!csb0_reg && web0_reg) + dout0 <= #(DELAY) mem[addr0_reg]; end - endmodule diff --git a/compiler/tests/golden/sram_2_16_2_scn4m_subm_1bank.v b/compiler/tests/golden/sram_2_16_2_scn4m_subm_1bank.v deleted file mode 100644 index 1e6a2722..00000000 --- a/compiler/tests/golden/sram_2_16_2_scn4m_subm_1bank.v +++ /dev/null @@ -1,73 +0,0 @@ -// OpenRAM SRAM model -// Words: 16 -// Word size: 2 - -module sram_2_16_2_scn4m_subm_1bank( -`ifdef USE_POWER_PINS - vdd, - gnd, -`endif -// Port 0: RW - clk0,csb0,web0,addr0,din0,dout0 - ); - - parameter DATA_WIDTH = 2 ; - parameter ADDR_WIDTH = 3 ; - parameter RAM_DEPTH = 1 << ADDR_WIDTH; - // FIXME: This delay is arbitrary. - parameter DELAY = 3 ; - parameter VERBOSE = 1 ; //Set to 0 to only display warnings - parameter T_HOLD = 1 ; //Delay to hold dout value after posedge. Value is arbitrary - -`ifdef USE_POWER_PINS - inout vdd; - inout gnd; -`endif - input clk0; // clock - input csb0; // active low chip select - input web0; // active low write control - input [ADDR_WIDTH-1:0] addr0; - input [DATA_WIDTH-1:0] din0; - output [DATA_WIDTH-1:0] dout0; - - reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1]; - - reg csb0_reg; - reg web0_reg; - reg [ADDR_WIDTH-1:0] addr0_reg; - reg [DATA_WIDTH-1:0] din0_reg; - reg [DATA_WIDTH-1:0] dout0; - - // All inputs are registers - always @(posedge clk0) - begin - csb0_reg = csb0; - web0_reg = web0; - addr0_reg = addr0; - din0_reg = din0; - #(T_HOLD) dout0 = 2'bx; - if ( !csb0_reg && web0_reg && VERBOSE ) - $display($time," Reading %m addr0=%b dout0=%b",addr0_reg,mem[addr0_reg]); - if ( !csb0_reg && !web0_reg && VERBOSE ) - $display($time," Writing %m addr0=%b din0=%b",addr0_reg,din0_reg); - end - - - // Memory Write Block Port 0 - // Write Operation : When web0 = 0, csb0 = 0 - always @ (negedge clk0) - begin : MEM_WRITE0 - if ( !csb0_reg && !web0_reg ) begin - mem[addr0_reg][1:0] = din0_reg[1:0]; - end - end - - // Memory Read Block Port 0 - // Read Operation : When web0 = 1, csb0 = 0 - always @ (negedge clk0) - begin : MEM_READ0 - if (!csb0_reg && web0_reg) - dout0 <= #(DELAY) mem[addr0_reg]; - end - -endmodule diff --git a/compiler/tests/golden/sram_2_16_2_scn4m_subm_top.v b/compiler/tests/golden/sram_2_16_2_scn4m_subm_top.v new file mode 100644 index 00000000..e52084d9 --- /dev/null +++ b/compiler/tests/golden/sram_2_16_2_scn4m_subm_top.v @@ -0,0 +1,105 @@ + +module sram_2_16_2_scn4m_subm_top ( +`ifdef USE_POWER_PINS + vdd, + gnd, +`endif + clk0, + addr0, + din0, + csb0, + web0, + dout0 + ); + + parameter DATA_WIDTH = 2; + parameter ADDR_WIDTH= 4; + + parameter BANK_SEL = 1; + parameter NUM_WMASK = 0; + +`ifdef USE_POWER_PINS + inout vdd; + inout gnd; +`endif + input clk0; + input [ADDR_WIDTH - 1 : 0] addr0; + input [DATA_WIDTH - 1: 0] din0; + input csb0; + input web0; + output reg [DATA_WIDTH - 1 : 0] dout0; + + reg [BANK_SEL - 1 : 0] addr0_reg; + + wire [DATA_WIDTH - 1 : 0] dout0_bank0; + + reg web0_bank0; + + reg csb0_bank0; + + wire [DATA_WIDTH - 1 : 0] dout0_bank1; + + reg web0_bank1; + + reg csb0_bank1; + + + sram_2_16_2_scn4m_subm bank0 ( +`ifdef USE_POWER_PINS + .vdd(vdd), + .gnd(gnd), +`endif + .clk0(clk0), + .addr0(addr0[ADDR_WIDTH - BANK_SEL - 1 : 0]), + .din0(din0), + .csb0(csb0_bank0), + .web0(web0_bank0), + .dout0(dout0_bank0) + ); + sram_2_16_2_scn4m_subm bank1 ( +`ifdef USE_POWER_PINS + .vdd(vdd), + .gnd(gnd), +`endif + .clk0(clk0), + .addr0(addr0[ADDR_WIDTH - BANK_SEL - 1 : 0]), + .din0(din0), + .csb0(csb0_bank1), + .web0(web0_bank1), + .dout0(dout0_bank1) + ); + + always @(posedge clk0) begin + addr0_reg <= addr0[ADDR_WIDTH - 1 : ADDR_WIDTH - BANK_SEL]; + end + + always @(*) begin + case (addr0_reg) + 0: begin + dout0 = dout0_bank0; + end + 1: begin + dout0 = dout0_bank1; + end + endcase + end + + always @(*) begin + csb0_bank0 = 1'b1; + web0_bank0 = 1'b1; + csb0_bank1 = 1'b1; + web0_bank1 = 1'b1; + case (addr0[ADDR_WIDTH - 1 : ADDR_WIDTH - BANK_SEL]) + 0: begin + web0_bank0 = web0; + csb0_bank0 = csb0; + end + 1: begin + web0_bank1 = web0; + csb0_bank1 = csb0; + end + endcase + end + + +endmodule