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Added more accurate bitline delay capacitance estimations

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Hunter Nichols
2019-04-09 01:56:32 -07:00
parent 1438519495
commit 25c034f85d
7 changed files with 21 additions and 25 deletions
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technology/freepdk45/tech/tech.py
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@@ -349,6 +349,7 @@ parameter["sa_en_nmos_size"] = .27 #micro-meters
parameter["sa_inv_pmos_size"] = .54 #micro-meters
parameter["sa_inv_nmos_size"] = .27 #micro-meters
parameter["rbl_height_percentage"] = .5 #Height of RBL compared to bitcell array
parameter['bitcell_drain_cap'] = 0.1 #In Femto-Farad, approximation of drain capacitance
###################################################
##END Spice Simulation Parameters
technology/scn4m_subm/tech/tech.py
+1
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@@ -315,6 +315,7 @@ parameter["sa_en_nmos_size"] = 9*_lambda_
parameter["sa_inv_pmos_size"] = 18*_lambda_
parameter["sa_inv_nmos_size"] = 9*_lambda_
parameter["rbl_height_percentage"] = .5 #Height of RBL compared to bitcell array
parameter['bitcell_drain_cap'] = 0.2 #In Femto-Farad, approximation of drain capacitance
###################################################
##END Spice Simulation Parameters