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OpenRAM
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add trailing 0 to web

This commit is contained in:
Michael Timothy Grimes 2018-09-09 15:16:53 -07:00
parent 68c00d7467
commit 252ae1effa
1 changed files with 2 additions and 2 deletions
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4
compiler/modules/control_logic.py
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@ -96,7 +96,7 @@ class control_logic(design.design):
""" Setup bus names, determine the size of the busses etc """ """ Setup bus names, determine the size of the busses etc """
# List of input control signals # List of input control signals
self.input_list =["csb","web"] self.input_list =["csb","web0"]
self.dff_output_list =["cs_bar", "cs", "we_bar", "we"] self.dff_output_list =["cs_bar", "cs", "we_bar", "we"]
# list of output control signals (for making a vertical bus) # list of output control signals (for making a vertical bus)
self.internal_bus_list = ["clk_buf", "clk_buf_bar", "we", "cs"] self.internal_bus_list = ["clk_buf", "clk_buf_bar", "we", "cs"]
@ -275,7 +275,7 @@ class control_logic(design.design):
rotate=90) rotate=90)
self.copy_layout_pin(self.ctrl_dff_inst, "din[0]", "csb") self.copy_layout_pin(self.ctrl_dff_inst, "din[0]", "csb")
self.copy_layout_pin(self.ctrl_dff_inst, "din[1]", "web") self.copy_layout_pin(self.ctrl_dff_inst, "din[1]", "web0")
def create_dffs(self): def create_dffs(self):