From 252ae1effa96a1275dc34fcb6382ed3be5e5ac63 Mon Sep 17 00:00:00 2001 From: Michael Timothy Grimes Date: Sun, 9 Sep 2018 15:16:53 -0700 Subject: [PATCH] add trailing 0 to web --- compiler/modules/control_logic.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index 02504313..7055797e 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -96,7 +96,7 @@ class control_logic(design.design): """ Setup bus names, determine the size of the busses etc """ # List of input control signals - self.input_list =["csb","web"] + self.input_list =["csb","web0"] self.dff_output_list =["cs_bar", "cs", "we_bar", "we"] # list of output control signals (for making a vertical bus) self.internal_bus_list = ["clk_buf", "clk_buf_bar", "we", "cs"] @@ -275,7 +275,7 @@ class control_logic(design.design): rotate=90) self.copy_layout_pin(self.ctrl_dff_inst, "din[0]", "csb") - self.copy_layout_pin(self.ctrl_dff_inst, "din[1]", "web") + self.copy_layout_pin(self.ctrl_dff_inst, "din[1]", "web0") def create_dffs(self):