From 24bfaa3b76e889ea94bab17012c111d45ddc70a1 Mon Sep 17 00:00:00 2001 From: jsowash Date: Fri, 5 Jul 2019 15:55:03 -0700 Subject: [PATCH] Added write_size to test 16 and added a newline to Verilog with no wmask for test 25. --- compiler/base/verilog.py | 2 ++ compiler/tests/16_control_logic_multiport_test.py | 6 +++--- compiler/tests/16_control_logic_test.py | 2 +- 3 files changed, 6 insertions(+), 4 deletions(-) diff --git a/compiler/base/verilog.py b/compiler/base/verilog.py index f1e5cd13..5489a3cd 100644 --- a/compiler/base/verilog.py +++ b/compiler/base/verilog.py @@ -28,6 +28,8 @@ class verilog: self.vf.write("// Word size: {0}\n".format(self.word_size)) if self.wmask_enabled: self.vf.write("// Write size: {0}\n\n".format(self.write_size)) + else: + self.vf.write("\n") self.vf.write("module {0}(\n".format(self.name)) for port in self.all_ports: diff --git a/compiler/tests/16_control_logic_multiport_test.py b/compiler/tests/16_control_logic_multiport_test.py index 66c34d24..3ad898b1 100755 --- a/compiler/tests/16_control_logic_multiport_test.py +++ b/compiler/tests/16_control_logic_multiport_test.py @@ -34,19 +34,19 @@ class control_logic_test(openram_test): OPTS.num_r_ports = 1 debug.info(1, "Testing sample for control_logic for multiport, only write control logic") - a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=8, port_type="rw") + a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=8, write_size=8, port_type="rw") self.local_check(a) # OPTS.num_rw_ports = 0 # OPTS.num_w_ports = 1 debug.info(1, "Testing sample for control_logic for multiport, only write control logic") - a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=8, port_type="w") + a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=8, write_size=8, port_type="w") self.local_check(a) # OPTS.num_w_ports = 0 # OPTS.num_r_ports = 1 debug.info(1, "Testing sample for control_logic for multiport, only read control logic") - a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=8, port_type="r") + a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=8, write_size=8, port_type="r") self.local_check(a) globals.end_openram() diff --git a/compiler/tests/16_control_logic_test.py b/compiler/tests/16_control_logic_test.py index 2be0bf0f..13e6c46c 100755 --- a/compiler/tests/16_control_logic_test.py +++ b/compiler/tests/16_control_logic_test.py @@ -24,7 +24,7 @@ class control_logic_test(openram_test): # check control logic for single port debug.info(1, "Testing sample for control_logic") - a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=32) + a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=32, write_size=32) self.local_check(a) # run the test from the command line