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Route bl in SRAM write ports too

This commit is contained in:
Matt Guthaus 2019-08-10 12:53:07 -07:00
parent 34d28a19e6
commit 23676c0f37
1 changed files with 1 additions and 1 deletions
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2
compiler/sram/sram_1bank.py
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@ -301,7 +301,7 @@ class sram_1bank(sram_base):
dest_pin = self.bank_inst.get_pin(signal+"{}".format(port)) dest_pin = self.bank_inst.get_pin(signal+"{}".format(port))
self.connect_vbus_m2m3(src_pin, dest_pin) self.connect_vbus_m2m3(src_pin, dest_pin)
for port in self.read_ports: for port in self.all_ports:
# Only input (besides pins) is the replica bitline # Only input (besides pins) is the replica bitline
src_pin = self.control_logic_insts[port].get_pin("rbl_bl") src_pin = self.control_logic_insts[port].get_pin("rbl_bl")
dest_pin = self.bank_inst.get_pin("rbl_bl{}".format(port)) dest_pin = self.bank_inst.get_pin("rbl_bl{}".format(port))