From 23676c0f374eeada21d2f55135ddc6bbeb4ea662 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Sat, 10 Aug 2019 12:53:07 -0700 Subject: [PATCH] Route bl in SRAM write ports too --- compiler/sram/sram_1bank.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/sram/sram_1bank.py b/compiler/sram/sram_1bank.py index 355ca769..51cfeada 100644 --- a/compiler/sram/sram_1bank.py +++ b/compiler/sram/sram_1bank.py @@ -301,7 +301,7 @@ class sram_1bank(sram_base): dest_pin = self.bank_inst.get_pin(signal+"{}".format(port)) self.connect_vbus_m2m3(src_pin, dest_pin) - for port in self.read_ports: + for port in self.all_ports: # Only input (besides pins) is the replica bitline src_pin = self.control_logic_insts[port].get_pin("rbl_bl") dest_pin = self.bank_inst.get_pin("rbl_bl{}".format(port))