From 22c821f5d868865910d4bffb82f8e23a0bf01373 Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 23 Jun 2020 15:40:00 -0700 Subject: [PATCH] Change port_address test to 256 for riscv --- compiler/tests/18_port_address_1rw_1r_test.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/compiler/tests/18_port_address_1rw_1r_test.py b/compiler/tests/18_port_address_1rw_1r_test.py index ff09dec9..caf2cb96 100755 --- a/compiler/tests/18_port_address_1rw_1r_test.py +++ b/compiler/tests/18_port_address_1rw_1r_test.py @@ -30,8 +30,8 @@ class port_address_1rw_1r_test(openram_test): a = factory.create("port_address", cols=16, rows=16) self.local_check(a) - debug.info(1, "Port address 512 rows") - a = factory.create("port_address", cols=256, rows=512) + debug.info(1, "Port address 256 rows") + a = factory.create("port_address", cols=256, rows=256) self.local_check(a) globals.end_openram()