mirror of https://github.com/VLSIDA/OpenRAM.git
Add perimeter margin to expand pins outside perimeter for OpenRoad router.
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5843aa037c
commit
229b0059c4
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@ -28,7 +28,7 @@ class router(router_tech):
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route on a given layer. This is limited to two layer routes.
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route on a given layer. This is limited to two layer routes.
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It populates blockages on a grid class.
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It populates blockages on a grid class.
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"""
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"""
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def __init__(self, layers, design, gds_filename=None, bbox=None, route_track_width=1):
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def __init__(self, layers, design, gds_filename=None, bbox=None, margin=0, route_track_width=1):
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"""
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"""
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This will instantiate a copy of the gds file or the module at (0,0) and
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This will instantiate a copy of the gds file or the module at (0,0) and
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route on top of this. The blockages from the gds/module will be
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route on top of this. The blockages from the gds/module will be
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@ -83,9 +83,11 @@ class router(router_tech):
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# A list of path blockages (they might be expanded for wide metal DRC)
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# A list of path blockages (they might be expanded for wide metal DRC)
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self.path_blockages = []
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self.path_blockages = []
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self.init_bbox(bbox)
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# The perimeter pins should be placed outside the SRAM macro by a distance
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self.margin = margin
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self.init_bbox(bbox, margin)
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def init_bbox(self, bbox=None):
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def init_bbox(self, bbox=None, margin=0):
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"""
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"""
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Initialize the ll,ur values with the paramter or using the layout boundary.
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Initialize the ll,ur values with the paramter or using the layout boundary.
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"""
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"""
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@ -99,18 +101,19 @@ class router(router_tech):
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else:
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else:
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self.ll, self.ur = bbox
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self.ll, self.ur = bbox
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self.bbox = (self.ll, self.ur)
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margin_offset = vector(margin, margin)
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self.bbox = (self.ll - margin_offset, self.ur + margin_offset)
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size = self.ur - self.ll
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size = self.ur - self.ll
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debug.info(1, "Size: {0} x {1}".format(size.x, size.y))
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debug.info(1, "Size: {0} x {1} with perimeter margin {2}".format(size.x, size.y, margin))
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def get_bbox(self):
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def get_bbox(self):
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return self.bbox
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return self.bbox
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def create_routing_grid(self, router_type, bbox=None):
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def create_routing_grid(self, router_type):
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"""
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"""
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Create a sprase routing grid with A* expansion functions.
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Create a sprase routing grid with A* expansion functions.
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"""
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"""
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self.init_bbox(bbox)
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self.init_bbox(self.bbox, self.margin)
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self.rg = router_type(self.ll, self.ur, self.track_width)
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self.rg = router_type(self.ll, self.ur, self.track_width)
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def clear_pins(self):
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def clear_pins(self):
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@ -17,12 +17,17 @@ class signal_escape_router(router):
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A router that routes signals to perimeter and makes pins.
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A router that routes signals to perimeter and makes pins.
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"""
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"""
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def __init__(self, layers, design, bbox=None, gds_filename=None):
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def __init__(self, layers, design, bbox=None, margin=0, gds_filename=None):
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"""
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"""
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This will route on layers in design. It will get the blockages from
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This will route on layers in design. It will get the blockages from
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either the gds file name or the design itself (by saving to a gds file).
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either the gds file name or the design itself (by saving to a gds file).
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"""
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"""
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router.__init__(self, layers, design, gds_filename, bbox)
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router.__init__(self,
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layers=layers,
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design=design,
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gds_filename=gds_filename,
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bbox=bbox,
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margin=margin)
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def perimeter_dist(self, pin_name):
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def perimeter_dist(self, pin_name):
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"""
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"""
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@ -54,8 +59,8 @@ class signal_escape_router(router):
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start_time = datetime.now()
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start_time = datetime.now()
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for pin_name in ordered_pin_names:
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for pin_name in ordered_pin_names:
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self.route_signal(pin_name)
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self.route_signal(pin_name)
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#if pin_name == "dout1[1]":
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# if pin_name == "dout0[1]":
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# self.write_debug_gds("postroute.gds", False)
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# self.write_debug_gds("postroute.gds", True)
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print_time("Maze routing pins",datetime.now(), start_time, 3)
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print_time("Maze routing pins",datetime.now(), start_time, 3)
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@ -306,7 +306,9 @@ class sram_base(design, verilog, lef):
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pins_to_route.append("spare_wen{0}[{1}]".format(port, bit))
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pins_to_route.append("spare_wen{0}[{1}]".format(port, bit))
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from signal_escape_router import signal_escape_router as router
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from signal_escape_router import signal_escape_router as router
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rtr=router(self.m3_stack, self)
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rtr=router(layers=self.m3_stack,
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design=self,
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margin=4 * self.m3_pitch)
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rtr.escape_route(pins_to_route)
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rtr.escape_route(pins_to_route)
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def compute_bus_sizes(self):
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def compute_bus_sizes(self):
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