From 229b0059c4035b3a6c0e5a7e6d59e8ce3531222f Mon Sep 17 00:00:00 2001
From: mrg <mrg@ucsc.edu>
Date: Wed, 7 Apr 2021 12:17:16 -0700
Subject: [PATCH] Add perimeter margin to expand pins outside perimeter for
 OpenRoad router.

---
 compiler/router/router.py               | 17 ++++++++++-------
 compiler/router/signal_escape_router.py | 13 +++++++++----
 compiler/sram/sram_base.py              |  4 +++-
 3 files changed, 22 insertions(+), 12 deletions(-)

diff --git a/compiler/router/router.py b/compiler/router/router.py
index dc0c8e8d..aa01c71f 100644
--- a/compiler/router/router.py
+++ b/compiler/router/router.py
@@ -28,7 +28,7 @@ class router(router_tech):
     route on a given layer. This is limited to two layer routes.
     It populates blockages on a grid class.
     """
-    def __init__(self, layers, design, gds_filename=None, bbox=None, route_track_width=1):
+    def __init__(self, layers, design, gds_filename=None, bbox=None, margin=0, route_track_width=1):
         """
         This will instantiate a copy of the gds file or the module at (0,0) and
         route on top of this. The blockages from the gds/module will be
@@ -83,9 +83,11 @@ class router(router_tech):
         # A list of path blockages (they might be expanded for wide metal DRC)
         self.path_blockages = []
 
-        self.init_bbox(bbox)
+        # The perimeter pins should be placed outside the SRAM macro by a distance
+        self.margin = margin
+        self.init_bbox(bbox, margin)
 
-    def init_bbox(self, bbox=None):
+    def init_bbox(self, bbox=None, margin=0):
         """
         Initialize the ll,ur values with the paramter or using the layout boundary.
         """
@@ -99,18 +101,19 @@ class router(router_tech):
         else:
             self.ll, self.ur = bbox
 
-        self.bbox = (self.ll, self.ur)
+        margin_offset = vector(margin, margin)
+        self.bbox = (self.ll - margin_offset, self.ur + margin_offset)
         size = self.ur - self.ll
-        debug.info(1, "Size: {0} x {1}".format(size.x, size.y))
+        debug.info(1, "Size: {0} x {1} with perimeter margin {2}".format(size.x, size.y, margin))
         
     def get_bbox(self):
         return self.bbox
     
-    def create_routing_grid(self, router_type, bbox=None):
+    def create_routing_grid(self, router_type):
         """
         Create a sprase routing grid with A* expansion functions.
         """
-        self.init_bbox(bbox)
+        self.init_bbox(self.bbox, self.margin)
         self.rg = router_type(self.ll, self.ur, self.track_width)
 
     def clear_pins(self):
diff --git a/compiler/router/signal_escape_router.py b/compiler/router/signal_escape_router.py
index 846925bd..a9531290 100644
--- a/compiler/router/signal_escape_router.py
+++ b/compiler/router/signal_escape_router.py
@@ -17,12 +17,17 @@ class signal_escape_router(router):
     A router that routes signals to perimeter and makes pins.
     """
 
-    def __init__(self, layers, design, bbox=None, gds_filename=None):
+    def __init__(self, layers, design, bbox=None, margin=0, gds_filename=None):
         """
         This will route on layers in design. It will get the blockages from
         either the gds file name or the design itself (by saving to a gds file).
         """
-        router.__init__(self, layers, design, gds_filename, bbox)
+        router.__init__(self,
+                        layers=layers,
+                        design=design,
+                        gds_filename=gds_filename,
+                        bbox=bbox,
+                        margin=margin)
 
     def perimeter_dist(self, pin_name):
         """
@@ -54,8 +59,8 @@ class signal_escape_router(router):
         start_time = datetime.now()
         for pin_name in ordered_pin_names:
             self.route_signal(pin_name)
-            #if pin_name == "dout1[1]":
-            #    self.write_debug_gds("postroute.gds", False)
+            # if pin_name == "dout0[1]":
+            #     self.write_debug_gds("postroute.gds", True)
             
         print_time("Maze routing pins",datetime.now(), start_time, 3)
 
diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py
index b683dbbc..fa0692e0 100644
--- a/compiler/sram/sram_base.py
+++ b/compiler/sram/sram_base.py
@@ -306,7 +306,9 @@ class sram_base(design, verilog, lef):
                     pins_to_route.append("spare_wen{0}[{1}]".format(port, bit))
 
         from signal_escape_router import signal_escape_router as router
-        rtr=router(self.m3_stack, self)
+        rtr=router(layers=self.m3_stack,
+                   design=self,
+                   margin=4 * self.m3_pitch)
         rtr.escape_route(pins_to_route)
 
     def compute_bus_sizes(self):