Add SCMOS library file generation.

lib/freepdk45/Makefile

@@ -25,6 +25,6 @@ OPTS = -c
 	mv $(bname)*.lib lib
 
 clean:
-	rm -f *.log *.pyc *~ *.gds *.lib *.sp *.v *.lef
+	rm -f *.log configs/*.pyc *~ *.gds *.lib *.sp *.v *.lef
 	rm -f gds/* lef/* lib/* sp/* verilog/*
 

lib/scn3me_subm/Makefile

@@ -0,0 +1,30 @@
+CUR_DIR = $(shell pwd)
+TEST_DIR = ${CUR_DIR}/tests
+
+MAKEFLAGS += -j 2
+
+CONFIG_DIR = configs
+OUT_DIRS = sp lib lef gds  verilog
+$(shell   mkdir -p $(OUT_DIRS))
+
+SRCS=$(wildcard $(CONFIG_DIR)/*.py)
+SPICES=$(SRCS:.py=.sp)
+all : $(SPICES) 
+
+# Characterize and perform DRC/LVS
+OPTS = -c
+# Do not characterize or perform DRC/LVS
+#OPTS = -n
+%.sp : %.py
+	$(eval bname=$(basename $(notdir $<)))
+	openram.py $(OPTS) $< 2>&1 > $(bname).log
+	mv $(bname).lef lef
+	mv $(bname).v verilog
+	mv $(bname).sp sp
+	mv $(bname).gds gds
+	mv $(bname)*.lib lib
+
+clean:
+	rm -f *.log configs/*.pyc *~ *.gds *.lib *.sp *.v *.lef
+	rm -f gds/* lef/* lib/* sp/* verilog/*
+

lib/scn3me_subm/configs/sram_1rw_128b_1024w_1bank_scn3me_subm.py

@@ -0,0 +1,5 @@
+word_size = 128
+num_words = 1024
+num_banks = 1
+
+tech_name = "scn3me_subm"

lib/scn3me_subm/configs/sram_1rw_32b_1024w_1bank_scn3me_subm.py

@@ -0,0 +1,5 @@
+word_size = 32
+num_words = 1024
+num_banks = 1
+
+tech_name = "scn3me_subm"

lib/scn3me_subm/configs/sram_1rw_32b_2048w_1bank_scn3me_subm.py

@@ -0,0 +1,5 @@
+word_size = 32
+num_words = 2048
+num_banks = 1
+
+tech_name = "scn3me_subm"

lib/scn3me_subm/configs/sram_1rw_8b_1024w_4bank_scn3me_subm.py

@@ -0,0 +1,5 @@
+word_size = 8
+num_words = 1024
+num_banks = 4
+
+tech_name = "scn3me_subm"

lib/scn3me_subm/configs/sram_1rw_8b_256w_1bank_scn3me_subm.py

@@ -0,0 +1,5 @@
+word_size = 8
+num_words = 256
+num_banks = 1
+
+tech_name = "scn3me_subm"

lib/scn3me_subm/configs/sram_1rw_8b_512w_4bank_scn3me_subm.py

@@ -0,0 +1,5 @@
+word_size = 8
+num_words = 512
+num_banks = 4
+
+tech_name = "scn3me_subm"