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Update TODO list

This commit is contained in:
Matt Guthaus 2016-11-09 11:38:36 -08:00
parent db8a675d90
commit 1fdb0ba5fc
1 changed files with 1 additions and 5 deletions
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@ -1,7 +1,4 @@
Develop set of vector/point manipulation functions and replace
everywhere. (Bin)
Use signal names from the technology file. Right now they are hard Use signal names from the technology file. Right now they are hard
coded everywhere. For example: DATA, ADDR, etc. coded everywhere. For example: DATA, ADDR, etc.
@ -17,7 +14,7 @@ the tech file.
Some modules use upper/lower via layer instead of min width DRC rule Some modules use upper/lower via layer instead of min width DRC rule
from tech file. from tech file.
Fix the size of labels. For some reason, they are HUGE. (Samira) Fix the size of the labels in freepdk45. They are ok in scn3me_subm though.
Add the clock buffer internal to control logic. Simulation uses Add the clock buffer internal to control logic. Simulation uses
1-4-8-16 inverters right now. Replace simulation with simple clock 1-4-8-16 inverters right now. Replace simulation with simple clock
@ -31,4 +28,3 @@ hierarchical_predecode3x8 to hierarchical_predecode class
Fix stimuli.py to be more readable. Fix stimuli.py to be more readable.
Add tests for bitcell, ms_flop, replica_bitcell, sens_amp, tri_gate, write_driver?