From 1fdb0ba5fcf44131ed3a2ad64d4d73d690d4ec5d Mon Sep 17 00:00:00 2001
From: Matt Guthaus <mrg@ucsc.edu>
Date: Wed, 9 Nov 2016 11:38:36 -0800
Subject: [PATCH] Update TODO list

---
 compiler/TODO | 6 +-----
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/compiler/TODO b/compiler/TODO
index e8744aaa..31cde6d5 100644
--- a/compiler/TODO
+++ b/compiler/TODO
@@ -1,7 +1,4 @@
 
-Develop set of vector/point manipulation functions and replace
-everywhere. (Bin)
-
 Use signal names from the technology file. Right now they are hard
 coded everywhere. For example: DATA, ADDR, etc.
 
@@ -17,7 +14,7 @@ the tech file.
 Some modules use upper/lower via layer instead of min width DRC rule
 from tech file.
 
-Fix the size of labels. For some reason, they are HUGE. (Samira)
+Fix the size of the labels in freepdk45. They are ok in scn3me_subm though.
 
 Add the clock buffer internal to control logic. Simulation uses
 1-4-8-16 inverters right now.  Replace simulation with simple clock
@@ -31,4 +28,3 @@ hierarchical_predecode3x8 to hierarchical_predecode class
 
 Fix stimuli.py to be more readable.
 
-Add tests for bitcell, ms_flop, replica_bitcell, sens_amp, tri_gate, write_driver?