diff --git a/compiler/pgates/pand4.py b/compiler/pgates/pand4.py new file mode 100644 index 00000000..54d2890e --- /dev/null +++ b/compiler/pgates/pand4.py @@ -0,0 +1,165 @@ +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import debug +from vector import vector +import pgate +from sram_factory import factory + + +class pand4(pgate.pgate): + """ + This is a simple buffer used for driving loads. + """ + def __init__(self, name, size=1, height=None, vertical=False, add_wells=True): + debug.info(1, "Creating pand4 {}".format(name)) + self.add_comment("size: {}".format(size)) + + self.vertical = vertical + self.size = size + + # Creates the netlist and layout + super().__init__(name, height, add_wells) + + def create_netlist(self): + self.add_pins() + self.create_modules() + self.create_insts() + + def create_modules(self): + # Shield the cap, but have at least a stage effort of 4 + self.nand = factory.create(module_type="pnand4", + height=self.height, + add_wells=self.vertical) + + # Add the well tap to the inverter because when stacked + # vertically it is sometimes narrower + self.inv = factory.create(module_type="pdriver", + size_list=[self.size], + height=self.height, + add_wells=self.add_wells) + + self.add_mod(self.nand) + self.add_mod(self.inv) + + def create_layout(self): + if self.vertical: + self.height = 2 * self.nand.height + self.width = max(self.nand.width, self.inv.width) + else: + self.width = self.nand.width + self.inv.width + + self.place_insts() + self.add_wires() + self.add_layout_pins() + self.route_supply_rails() + self.add_boundary() + self.DRC_LVS() + + def add_pins(self): + self.add_pin("A", "INPUT") + self.add_pin("B", "INPUT") + self.add_pin("C", "INPUT") + self.add_pin("D", "INPUT") + self.add_pin("Z", "OUTPUT") + self.add_pin("vdd", "POWER") + self.add_pin("gnd", "GROUND") + + def create_insts(self): + self.nand_inst = self.add_inst(name="pand4_nand", + mod=self.nand) + self.connect_inst(["A", "B", "C", "D", "zb_int", "vdd", "gnd"]) + + self.inv_inst = self.add_inst(name="pand4_inv", + mod=self.inv) + self.connect_inst(["zb_int", "Z", "vdd", "gnd"]) + + def place_insts(self): + # Add NAND to the right + self.nand_inst.place(offset=vector(0, 0)) + + if self.vertical: + # Add INV above + self.inv_inst.place(offset=vector(self.inv.width, + 2 * self.nand.height), + mirror="XY") + else: + # Add INV to the right + self.inv_inst.place(offset=vector(self.nand_inst.rx(), 0)) + + def route_supply_rails(self): + """ Add vdd/gnd rails to the top, (middle), and bottom. """ + self.add_layout_pin_rect_center(text="gnd", + layer=self.route_layer, + offset=vector(0.5 * self.width, 0), + width=self.width) + + # Second gnd of the inverter gate + if self.vertical: + self.add_layout_pin_rect_center(text="gnd", + layer=self.route_layer, + offset=vector(0.5 * self.width, self.height), + width=self.width) + + if self.vertical: + # Shared between two gates + y_offset = 0.5 * self.height + else: + y_offset = self.height + self.add_layout_pin_rect_center(text="vdd", + layer=self.route_layer, + offset=vector(0.5 * self.width, y_offset), + width=self.width) + + def add_wires(self): + # nand Z to inv A + z1_pin = self.nand_inst.get_pin("Z") + a2_pin = self.inv_inst.get_pin("A") + if self.vertical: + route_layer = "m2" + self.add_via_stack_center(offset=z1_pin.center(), + from_layer=z1_pin.layer, + to_layer=route_layer) + self.add_zjog(route_layer, + z1_pin.uc(), + a2_pin.bc(), + "V") + self.add_via_stack_center(offset=a2_pin.center(), + from_layer=a2_pin.layer, + to_layer=route_layer) + else: + route_layer = self.route_layer + mid1_point = vector(z1_pin.cx(), a2_pin.cy()) + self.add_path(route_layer, + [z1_pin.center(), mid1_point, a2_pin.center()]) + + def add_layout_pins(self): + pin = self.inv_inst.get_pin("Z") + self.add_layout_pin_rect_center(text="Z", + layer=pin.layer, + offset=pin.center(), + width=pin.width(), + height=pin.height()) + + for pin_name in ["A", "B", "C"]: + pin = self.nand_inst.get_pin(pin_name) + self.add_layout_pin_rect_center(text=pin_name, + layer=pin.layer, + offset=pin.center(), + width=pin.width(), + height=pin.height()) + + def analytical_delay(self, corner, slew, load=0.0): + """ Calculate the analytical delay of DFF-> INV -> INV """ + nand_delay = self.nand.analytical_delay(corner, + slew=slew, + load=self.inv.input_load()) + inv_delay = self.inv.analytical_delay(corner, + slew=nand_delay.slew, + load=load) + return nand_delay + inv_delay + diff --git a/compiler/pgates/pnand3.py b/compiler/pgates/pnand3.py index efcbe369..db5a1f28 100644 --- a/compiler/pgates/pnand3.py +++ b/compiler/pgates/pnand3.py @@ -133,7 +133,6 @@ class pnand3(pgate.pgate): # This is the extra space needed to ensure DRC rules # to the active contacts nmos = factory.create(module_type="ptx", tx_type="nmos") - extra_contact_space = max(-nmos.get_pin("D").by(), 0) def create_ptx(self): """ diff --git a/compiler/pgates/pnand4.py b/compiler/pgates/pnand4.py new file mode 100644 index 00000000..ba909dce --- /dev/null +++ b/compiler/pgates/pnand4.py @@ -0,0 +1,372 @@ +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import pgate +import debug +from tech import drc, parameter, spice +from vector import vector +import logical_effort +from sram_factory import factory +from globals import OPTS +import contact + + +class pnand4(pgate.pgate): + """ + This module generates gds of a parametrically sized 4-input nand. + This model use ptx to generate a 4-input nand within a cetrain height. + """ + def __init__(self, name, size=1, height=None, add_wells=True): + """ Creates a cell for a simple 3 input nand """ + + debug.info(2, + "creating pnand4 structure {0} with size of {1}".format(name, + size)) + self.add_comment("size: {}".format(size)) + + # We have trouble pitch matching a 3x sizes to the bitcell... + # If we relax this, we could size this better. + self.size = size + self.nmos_size = 2 * size + self.pmos_size = parameter["beta"] * size + self.nmos_width = self.nmos_size * drc("minwidth_tx") + self.pmos_width = self.pmos_size * drc("minwidth_tx") + + # FIXME: Allow these to be sized + debug.check(size == 1, + "Size 1 pnand4 is only supported now.") + self.tx_mults = 1 + + if OPTS.tech_name == "sky130": + self.nmos_width = self.nearest_bin("nmos", self.nmos_width) + self.pmos_width = self.nearest_bin("pmos", self.pmos_width) + + # Creates the netlist and layout + super().__init__(name, height, add_wells) + + def add_pins(self): + """ Adds pins for spice netlist """ + pin_list = ["A", "B", "C", "D", "Z", "vdd", "gnd"] + dir_list = ["INPUT", "INPUT", "INPUT", "INPUT", "OUTPUT", "POWER", "GROUND"] + self.add_pin_list(pin_list, dir_list) + + def create_netlist(self): + self.add_pins() + self.add_ptx() + self.create_ptx() + + def create_layout(self): + """ Calls all functions related to the generation of the layout """ + + self.setup_layout_constants() + self.place_ptx() + if self.add_wells: + self.add_well_contacts() + self.route_inputs() + self.route_output() + self.determine_width() + self.route_supply_rails() + self.connect_rails() + self.extend_wells() + self.add_boundary() + + def add_ptx(self): + """ Create the PMOS and NMOS transistors. """ + self.nmos_center = factory.create(module_type="ptx", + width=self.nmos_width, + mults=self.tx_mults, + tx_type="nmos", + add_source_contact="active", + add_drain_contact="active") + self.add_mod(self.nmos_center) + + self.nmos_right = factory.create(module_type="ptx", + width=self.nmos_width, + mults=self.tx_mults, + tx_type="nmos", + add_source_contact="active", + add_drain_contact=self.route_layer) + self.add_mod(self.nmos_right) + + self.nmos_left = factory.create(module_type="ptx", + width=self.nmos_width, + mults=self.tx_mults, + tx_type="nmos", + add_source_contact=self.route_layer, + add_drain_contact="active") + self.add_mod(self.nmos_left) + + self.pmos_left = factory.create(module_type="ptx", + width=self.pmos_width, + mults=self.tx_mults, + tx_type="pmos", + add_source_contact=self.route_layer, + add_drain_contact=self.route_layer) + self.add_mod(self.pmos_left) + + self.pmos_center = factory.create(module_type="ptx", + width=self.pmos_width, + mults=self.tx_mults, + tx_type="pmos", + add_source_contact=self.route_layer, + add_drain_contact=self.route_layer) + self.add_mod(self.pmos_center) + + self.pmos_right = factory.create(module_type="ptx", + width=self.pmos_width, + mults=self.tx_mults, + tx_type="pmos", + add_source_contact=self.route_layer, + add_drain_contact=self.route_layer) + self.add_mod(self.pmos_right) + + def setup_layout_constants(self): + """ Pre-compute some handy layout parameters. """ + + # Compute the overlap of the source and drain pins + self.ptx_offset = self.pmos_left.get_pin("D").center() - self.pmos_left.get_pin("S").center() + + # This is the extra space needed to ensure DRC rules + # to the active contacts + nmos = factory.create(module_type="ptx", tx_type="nmos") + extra_contact_space = max(-nmos.get_pin("D").by(), 0) + + def create_ptx(self): + """ + Create the PMOS and NMOS in the netlist. + """ + + self.pmos1_inst = self.add_inst(name="pnand4_pmos1", + mod=self.pmos_left) + self.connect_inst(["vdd", "A", "Z", "vdd"]) + + self.pmos2_inst = self.add_inst(name="pnand4_pmos2", + mod=self.pmos_center) + self.connect_inst(["Z", "B", "vdd", "vdd"]) + + self.pmos3_inst = self.add_inst(name="pnand4_pmos3", + mod=self.pmos_center) + self.connect_inst(["Z", "C", "vdd", "vdd"]) + + self.pmos4_inst = self.add_inst(name="pnand4_pmos4", + mod=self.pmos_right) + self.connect_inst(["Z", "D", "vdd", "vdd"]) + + self.nmos1_inst = self.add_inst(name="pnand4_nmos1", + mod=self.nmos_left) + self.connect_inst(["Z", "D", "net1", "gnd"]) + + self.nmos2_inst = self.add_inst(name="pnand4_nmos2", + mod=self.nmos_center) + self.connect_inst(["net1", "C", "net2", "gnd"]) + + self.nmos3_inst = self.add_inst(name="pnand4_nmos3", + mod=self.nmos_center) + self.connect_inst(["net2", "B", "net3", "gnd"]) + + self.nmos4_inst = self.add_inst(name="pnand4_nmos4", + mod=self.nmos_right) + self.connect_inst(["net3", "A", "gnd", "gnd"]) + + def place_ptx(self): + """ + Place the PMOS and NMOS in the layout at the upper-most + and lowest position to provide maximum routing in channel + """ + + pmos1_pos = vector(self.pmos_left.active_offset.x, + self.height - self.pmos_left.active_height - self.top_bottom_space) + self.pmos1_inst.place(pmos1_pos) + + pmos2_pos = pmos1_pos + self.ptx_offset + self.pmos2_inst.place(pmos2_pos) + + pmos3_pos = pmos2_pos + self.ptx_offset + self.pmos3_inst.place(pmos3_pos) + + self.pmos4_pos = pmos3_pos + self.ptx_offset + self.pmos4_inst.place(self.pmos4_pos) + + nmos1_pos = vector(self.pmos_left.active_offset.x, + self.top_bottom_space) + self.nmos1_inst.place(nmos1_pos) + + nmos2_pos = nmos1_pos + self.ptx_offset + self.nmos2_inst.place(nmos2_pos) + + nmos3_pos = nmos2_pos + self.ptx_offset + self.nmos3_inst.place(nmos3_pos) + + self.nmos4_pos = nmos3_pos + self.ptx_offset + self.nmos4_inst.place(self.nmos4_pos) + + def add_well_contacts(self): + """ Add n/p well taps to the layout and connect to supplies """ + + self.add_nwell_contact(self.pmos_right, + self.pmos4_pos + vector(self.m1_pitch, 0)) + self.add_pwell_contact(self.nmos_right, + self.nmos4_pos + vector(self.m1_pitch, 0)) + + def connect_rails(self): + """ Connect the nmos and pmos to its respective power rails """ + + self.connect_pin_to_rail(self.nmos1_inst, "S", "gnd") + + self.connect_pin_to_rail(self.pmos1_inst, "S", "vdd") + + self.connect_pin_to_rail(self.pmos2_inst, "D", "vdd") + + self.connect_pin_to_rail(self.pmos4_inst, "D", "vdd") + + def route_inputs(self): + """ Route the A and B and C inputs """ + + # We can use this pitch because the contacts and overlap won't be adjacent + pmos_drain_bottom = self.pmos1_inst.get_pin("D").by() + self.output_yoffset = pmos_drain_bottom - 0.5 * self.route_layer_width - self.route_layer_space + + bottom_pin = self.nmos1_inst.get_pin("D") + # active contact metal to poly contact metal spacing + active_contact_to_poly_contact = bottom_pin.uy() + self.m1_space + 0.5 * contact.poly_contact.second_layer_height + # active diffusion to poly contact spacing + # doesn't use nmos uy because that is calculated using offset + poly height + active_top = self.nmos1_inst.by() + self.nmos1_inst.mod.active_height + active_to_poly_contact = active_top + self.poly_to_active + 0.5 * contact.poly_contact.first_layer_height + active_to_poly_contact2 = active_top + self.poly_contact_to_gate + 0.5 * self.route_layer_width + self.inputA_yoffset = max(active_contact_to_poly_contact, + active_to_poly_contact, + active_to_poly_contact2) + + apin = self.route_input_gate(self.pmos1_inst, + self.nmos1_inst, + self.inputA_yoffset, + "A", + position="left") + + self.inputB_yoffset = self.inputA_yoffset + self.m3_pitch + bpin = self.route_input_gate(self.pmos2_inst, + self.nmos2_inst, + self.inputB_yoffset, + "B", + position="center") + + self.inputC_yoffset = self.inputB_yoffset + self.m3_pitch + cpin = self.route_input_gate(self.pmos3_inst, + self.nmos3_inst, + self.inputC_yoffset, + "C", + position="right") + + self.inputD_yoffset = self.inputC_yoffset + self.m3_pitch + cpin = self.route_input_gate(self.pmos4_inst, + self.nmos4_inst, + self.inputD_yoffset, + "D", + position="right") + + if OPTS.tech_name == "sky130": + self.add_enclosure([apin, bpin, cpin], "npc", drc("npc_enclose_poly")) + + def route_output(self): + """ Route the Z output """ + + # PMOS1 drain + pmos1_pin = self.pmos1_inst.get_pin("D") + # PMOS3 drain + pmos3_pin = self.pmos3_inst.get_pin("D") + # NMOS3 drain + nmos4_pin = self.nmos4_inst.get_pin("D") + + out_offset = vector(nmos4_pin.cx() + self.route_layer_pitch, + self.output_yoffset) + + # Go up to metal2 for ease on all output pins + # self.add_via_center(layers=self.m1_stack, + # offset=pmos1_pin.center(), + # directions=("V", "V")) + # self.add_via_center(layers=self.m1_stack, + # offset=pmos3_pin.center(), + # directions=("V", "V")) + # self.add_via_center(layers=self.m1_stack, + # offset=nmos3_pin.center(), + # directions=("V", "V")) + + # # Route in the A input track (top track) + # mid_offset = vector(nmos3_pin.center().x, self.inputA_yoffset) + # self.add_path("m1", [pmos1_pin.center(), mid_offset, nmos3_pin.uc()]) + + # This extends the output to the edge of the cell + # self.add_via_center(layers=self.m1_stack, + # offset=mid_offset) + + top_left_pin_offset = pmos1_pin.center() + top_right_pin_offset = pmos3_pin.center() + bottom_pin_offset = nmos4_pin.center() + + # PMOS1 to output + self.add_path(self.route_layer, [top_left_pin_offset, + vector(top_left_pin_offset.x, out_offset.y), + out_offset]) + # PMOS4 to output + self.add_path(self.route_layer, [top_right_pin_offset, + vector(top_right_pin_offset.x, out_offset.y), + out_offset]) + # NMOS4 to output + mid2_offset = vector(out_offset.x, bottom_pin_offset.y) + self.add_path(self.route_layer, + [bottom_pin_offset, mid2_offset], + width=nmos4_pin.height()) + mid3_offset = vector(out_offset.x, nmos4_pin.by()) + self.add_path(self.route_layer, [mid3_offset, out_offset]) + + self.add_layout_pin_rect_center(text="Z", + layer=self.route_layer, + offset=out_offset) + + def analytical_power(self, corner, load): + """Returns dynamic and leakage power. Results in nW""" + c_eff = self.calculate_effective_capacitance(load) + freq = spice["default_event_frequency"] + power_dyn = self.calc_dynamic_power(corner, c_eff, freq) + power_leak = spice["nand4_leakage"] + + total_power = self.return_power(power_dyn, power_leak) + return total_power + + def calculate_effective_capacitance(self, load): + """Computes effective capacitance. Results in fF""" + c_load = load + # In fF + c_para = spice["min_tx_drain_c"] * (self.nmos_size / parameter["min_tx_size"]) + transition_prob = 0.1094 + return transition_prob * (c_load + c_para) + + def input_load(self): + """Return the relative input capacitance of a single input""" + return self.nmos_size + self.pmos_size + + def get_stage_effort(self, cout, inp_is_rise=True): + """ + Returns an object representing the parameters for delay in tau units. + Optional is_rise refers to the input direction rise/fall. + Input inverted by this stage. + """ + parasitic_delay = 3 + return logical_effort.logical_effort(self.name, + self.size, + self.input_load(), + cout, + parasitic_delay, + not inp_is_rise) + + def build_graph(self, graph, inst_name, port_nets): + """ + Adds edges based on inputs/outputs. + Overrides base class function. + """ + self.add_graph_edges(graph, port_nets) diff --git a/compiler/tests/04_pand2_test.py b/compiler/tests/04_pand2_test.py index f7e5f304..077c180e 100755 --- a/compiler/tests/04_pand2_test.py +++ b/compiler/tests/04_pand2_test.py @@ -8,13 +8,13 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS -from sram_factory import factory import debug + class pand2_test(openram_test): def runTest(self): diff --git a/compiler/tests/04_pand3_test.py b/compiler/tests/04_pand3_test.py index e58f1ee9..4817601e 100755 --- a/compiler/tests/04_pand3_test.py +++ b/compiler/tests/04_pand3_test.py @@ -8,13 +8,13 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS -from sram_factory import factory import debug + class pand3_test(openram_test): def runTest(self): diff --git a/compiler/tests/04_pand4_test.py b/compiler/tests/04_pand4_test.py new file mode 100755 index 00000000..f7dd329d --- /dev/null +++ b/compiler/tests/04_pand4_test.py @@ -0,0 +1,39 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys, os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +import debug + + +class pand4_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + global verify + import verify + + import pand4 + + debug.info(2, "Testing pand4 gate 4x") + a = pand4.pand4(name="pand4x4", size=4) + self.local_check(a) + + globals.end_openram() + +# instantiate a copdsay of the class to actually run the test +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/04_pnand4_test.py b/compiler/tests/04_pnand4_test.py new file mode 100755 index 00000000..d2c64a5b --- /dev/null +++ b/compiler/tests/04_pnand4_test.py @@ -0,0 +1,42 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys, os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + + +class pnand4_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + + debug.info(2, "Checking 4-input nand gate") + tx = factory.create(module_type="pnand4", size=1) + self.local_check(tx) + + # debug.info(2, "Checking 3-input nand gate") + # tx = factory.create(module_type="pnand3", size=1, add_wells=False) + # # Only DRC because well contacts will fail LVS + # self.local_drc_check(tx) + + globals.end_openram() + + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner())