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fix extra wl in col end, work on bring wl pins out to row end array, TODO: mirror alternating row end

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jcirimel
2020-10-08 05:32:03 -07:00
parent d40c3588ed
commit 1e7ae06b7e
8 changed files with 101 additions and 102 deletions
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compiler/tests/missing_pin.gds
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compiler/tests/sram_1b_16_1rw_sky130.log
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WARNING: file magic.py: line 210: DRC Errors replica_bitcell_array 985
WARNING: file magic.py: line 210: DRC Errors replica_bitcell_array 1010
ERROR: file magic.py: line 285: replica_bitcell_array LVS mismatch (results in /home/jesse/output/replica_bitcell_array.lvs.report)