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https://github.com/VLSIDA/OpenRAM.git
synced 2026-08-29 09:30:38 +02:00
fix extra wl in col end, work on bring wl pins out to row end array, TODO: mirror alternating row end
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jcirimel
@@ -64,7 +64,7 @@ class bitcell_base_array(design.design):
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else:
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self.wordline_names[port].append("wl0_{0}_{1}".format(port, row))
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self.wordline_names[port].append("wl1_{0}_{1}".format(port, row))
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self.all_wordline_names = [x for sl in zip(*self.wordline_names) for x in sl]
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def add_pins(self):
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@@ -147,32 +147,33 @@ class bitcell_base_array(design.design):
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def add_layout_pins(self):
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""" Add the layout pins """
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if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement):
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bitline_names = self.cell.get_all_bitline_names()
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for col in range(self.column_size):
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for port in self.all_ports:
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bl_pin = self.cell_inst[0, col].get_pin(bitline_names[2 * port])
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self.add_layout_pin(text="bl_{0}_{1}".format(port, col),
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layer=bl_pin.layer,
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offset=bl_pin.ll().scale(1, 0),
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width=bl_pin.width(),
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height=self.height)
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br_pin = self.cell_inst[0, col].get_pin(bitline_names[2 * port + 1])
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self.add_layout_pin(text="br_{0}_{1}".format(port, col),
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layer=br_pin.layer,
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offset=br_pin.ll().scale(1, 0),
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width=br_pin.width(),
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height=self.height)
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bitline_names = self.cell.get_all_bitline_names()
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for col in range(self.column_size):
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for port in self.all_ports:
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bl_pin = self.cell_inst[0, col].get_pin(bitline_names[2 * port])
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self.add_layout_pin(text="bl_{0}_{1}".format(port, col),
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layer=bl_pin.layer,
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offset=bl_pin.ll().scale(1, 0),
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width=bl_pin.width(),
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height=self.height)
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br_pin = self.cell_inst[0, col].get_pin(bitline_names[2 * port + 1])
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self.add_layout_pin(text="br_{0}_{1}".format(port, col),
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layer=br_pin.layer,
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offset=br_pin.ll().scale(1, 0),
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width=br_pin.width(),
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height=self.height)
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wl_names = self.cell.get_all_wl_names()
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for row in range(self.row_size):
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for port in self.all_ports:
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wl_pin = self.cell_inst[row, 0].get_pin(wl_names[port])
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self.add_layout_pin(text="wl_{0}_{1}".format(port, row),
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layer=wl_pin.layer,
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offset=wl_pin.ll().scale(0, 1),
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width=self.width,
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height=wl_pin.height())
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wl_names = self.cell.get_all_wl_names()
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for row in range(self.row_size):
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for port in self.all_ports:
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wl_pin = self.cell_inst[row, 0].get_pin(wl_names[port])
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self.add_layout_pin(text="wl_{0}_{1}".format(port, row),
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layer=wl_pin.layer,
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offset=wl_pin.ll().scale(0, 1),
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width=self.width,
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height=wl_pin.height())
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if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement):
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# Copy a vdd/gnd layout pin from every cell
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for row in range(self.row_size):
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@@ -181,37 +182,8 @@ class bitcell_base_array(design.design):
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for pin_name in ["vdd", "gnd"]:
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self.copy_layout_pin(inst, pin_name)
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else:
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bitline_names = self.cell.get_all_bitline_names()
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for col in range(self.column_size):
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for port in self.all_ports:
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bl_pin = self.cell_inst[0, col].get_pin(bitline_names[2 * port])
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self.add_layout_pin(text="bl0_{0}_{1}".format(port, col),
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layer=bl_pin.layer,
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offset=bl_pin.ll().scale(1, 0),
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width=bl_pin.width(),
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height=self.height)
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br_pin = self.cell_inst[0, col].get_pin(bitline_names[2 * port + 1])
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self.add_layout_pin(text="bl1_{0}_{1}".format(port, col),
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layer=br_pin.layer,
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offset=br_pin.ll().scale(1, 0),
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width=br_pin.width(),
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height=self.height)
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wl_names = self.cell.get_all_wl_names()
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for row in range(self.row_size):
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for port in self.all_ports:
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wl0_pin = self.cell_inst[row, 0].get_pin(wl_names[port])
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self.add_layout_pin(text="wl0_{0}_{1}".format(port, row),
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layer=wl0_pin.layer,
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offset=wl0_pin.ll().scale(0, 1),
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width=self.width,
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height=wl0_pin.height())
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wl1_pin = self.cell_inst[row, 0].get_pin(wl_names[port])
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self.add_layout_pin(text="wl1_{0}_{1}".format(port, row),
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layer=wl1_pin.layer,
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offset=wl1_pin.ll().scale(0, 1),
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width=self.width,
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height=wl1_pin.height())
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# Copy a vdd/gnd layout pin from every cell
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for row in range(self.row_size):
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for col in range(self.column_size):
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@@ -502,26 +502,18 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
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def add_layout_pins(self):
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""" Add the layout pins """
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# All wordlines
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# Main array wl and bl/br
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for pin_name in self.all_wordline_names:
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pin_list = self.bitcell_array_inst.get_pins(pin_name)
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for pin in pin_list:
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self.add_layout_pin(text=pin_name,
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layer=pin.layer,
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offset=pin.ll().scale(0, 1),
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width=self.width,
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height=pin.height())
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for pin_name in self.all_bitline_names:
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pin_list = self.bitcell_array_inst.get_pins(pin_name)
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for pin in pin_list:
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self.add_layout_pin(text=pin_name,
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layer=pin.layer,
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offset=pin.ll().scale(1, 0),
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width=pin.width(),
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height=self.height)
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#All wordlines
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#Main array wl and bl/br
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if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement):
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for pin_name in self.all_wordline_names:
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pin_list = self.bitcell_array_inst.get_pins(pin_name)
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for pin in pin_list:
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self.add_layout_pin(text=pin_name,
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layer=pin.layer,
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offset=pin.ll().scale(0, 1),
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width=self.width,
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height=pin.height())
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# Replica wordlines (go by the row instead of replica column because we may have to add a pin
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# even though the column is in another local bitcell array)
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for (names, inst) in zip(self.rbl_wordline_names, self.dummy_row_replica_insts):
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@@ -534,6 +526,36 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
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offset=pin.ll().scale(0, 1),
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width=self.width,
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height=pin.height())
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else:
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for pin_name in self.all_wordline_names:
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pin_list = self.dummy_col_insts[0].get_pins(pin_name)
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for pin in pin_list:
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self.add_layout_pin(text=pin_name,
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layer=pin.layer,
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offset=pin.ll().scale(0, 1),
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width=self.width,
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height=pin.height())
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# Replica wordlines (go by the row instead of replica column because we may have to add a pin
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# even though the column is in another local bitcell array)
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for (names, inst) in zip(self.rbl_wordline_names, self.dummy_row_replica_insts):
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for (wl_name, pin_name) in zip(names, self.dummy_row.get_wordline_names()):
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if wl_name in self.gnd_wordline_names:
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continue
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pin = inst.get_pin(pin_name)
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self.add_layout_pin(text=wl_name,
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layer=pin.layer,
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offset=pin.ll().scale(0, 1),
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width=self.width,
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height=pin.height())
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for pin_name in self.all_bitline_names:
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pin_list = self.bitcell_array_inst.get_pins(pin_name)
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for pin in pin_list:
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self.add_layout_pin(text=pin_name,
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layer=pin.layer,
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offset=pin.ll().scale(1, 0),
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width=pin.width(),
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height=self.height)
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# Replica bitlines
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if len(self.rbls) > 0:
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