Don't run lvs/drc or route supplies in verilog test

2026-09-03 08:27:11 +02:00 · 2020-04-02 12:42:28 -07:00
parent 67de7efd49
commit 1d5e5e3607
1 changed files with 3 additions and 1 deletions
@@ -19,7 +19,9 @@ class verilog_test(openram_test):
    def runTest(self):
        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
        globals.init_openram(config_file)
-
+        OPTS.route_supplies=False
+        OPTS.check_lvsdrc=False
+        
        from sram import sram
        from sram_config import sram_config
        c = sram_config(word_size=2,