Editting top level netlist for multiport. Now there are multiple control logic modules, one per port. Since diffent ports are driven by different clocks, also separating dff modules, one per port.

compiler/modules/bank.py

@@ -101,7 +101,7 @@ class bank(design.design):
             for port in range(self.total_ports):
                 self.add_pin("bank_sel{}".format(port),"INPUT")
         for port in range(self.total_read):
-            self.add_pin("s_en{0}".format(port), "INPUT")
+            self.add_pin("s_en{0}".format(self.read_index[port]), "INPUT")
         for port in range(self.total_write):
             self.add_pin("w_en{0}".format(port), "INPUT")
         for port in range(self.total_ports):
@@ -399,7 +399,7 @@ class bank(design.design):
                     temp.append(self.read_bl_list[port]+"_out[{0}]".format(bit))
                     temp.append(self.read_br_list[port]+"_out[{0}]".format(bit))
                     
-            temp.extend([self.prefix+"s_en{}".format(port), "vdd", "gnd"])
+            temp.extend([self.prefix+"s_en{}".format(self.read_index[port]), "vdd", "gnd"])
             self.connect_inst(temp)
 
             

compiler/modules/control_logic.py

@@ -20,8 +20,9 @@ class control_logic(design.design):
 
     def __init__(self, num_rows, port="rw"):
         """ Constructor """
-        design.design.__init__(self, "control_logic")
-        debug.info(1, "Creating {}".format(self.name))
+        name = "control_logic_" + port
+        design.design.__init__(self, name)
+        debug.info(1, "Creating {}".format(name))
         
         self.num_rows = num_rows
         self.port = port
@@ -95,7 +96,7 @@ class control_logic(design.design):
             delay_stages = 4 # Must be non-inverting
             delay_fanout = 3 # This can be anything >=2
             bitcell_loads = int(math.ceil(self.num_rows / 5.0))
-            self.replica_bitline = replica_bitline(delay_stages, delay_fanout, bitcell_loads)
+            self.replica_bitline = replica_bitline(delay_stages, delay_fanout, bitcell_loads, name="replica_bitline_"+self.port)
             self.add_mod(self.replica_bitline)
 
 

compiler/modules/delay_chain.py

@@ -13,8 +13,12 @@ class delay_chain(design.design):
     Usually, this will be constant, but it could have varied fanout.
     """
 
+    unique_id = 1
+
     def __init__(self, fanout_list, name="delay_chain"):
         """init function"""
+        name = name+"_{}".format(delay_chain.unique_id)
+        delay_chain.unique_id += 1
         design.design.__init__(self, name)
 
         # Two fanouts are needed so that we can route the vdd/gnd connections

compiler/modules/replica_bitline.py

@@ -81,8 +81,8 @@ class replica_bitline(design.design):
         """ Add the modules for later usage """
 
         from importlib import reload
-        g = reload(__import__(OPTS.delay_chain))
-        self.mod_delay_chain = getattr(g, OPTS.delay_chain)
+        #g = reload(__import__(OPTS.delay_chain))
+        #self.mod_delay_chain = getattr(g, OPTS.delay_chain)
 
         g = reload(__import__(OPTS.replica_bitcell))
         self.mod_replica_bitcell = getattr(g, OPTS.replica_bitcell)
@@ -95,7 +95,8 @@ class replica_bitline(design.design):
         self.add_mod(self.rbl)
 
         # FIXME: The FO and depth of this should be tuned
-        self.delay_chain = self.mod_delay_chain([self.delay_fanout]*self.delay_stages)
+        from delay_chain import delay_chain
+        self.delay_chain = delay_chain([self.delay_fanout]*self.delay_stages)
         self.add_mod(self.delay_chain)
 
         self.inv = pinv()