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Only add pins to periphery

This commit is contained in:
mrg 2020-06-29 10:03:24 -07:00
parent 5f3a45b91b
commit 1bc0775810
2 changed files with 6 additions and 17 deletions
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14
compiler/modules/replica_bitcell_array.py
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@ -378,16 +378,10 @@ class replica_bitcell_array(design.design):
width=pin.width(), width=pin.width(),
height=self.height) height=self.height)
# For specific technologies, there is no vdd via within the bitcell. Instead vdd is connect via end caps. # vdd/gnd are only connected in the perimeter cells
try: # replica column should only have a vdd/gnd in the dummy cell on top/bottom
if cell_properties.bitcell.end_caps_enabled: supply_insts = [self.dummy_col_left_inst, self.dummy_col_right_inst,
supply_insts = [self.dummy_col_left_inst, self.dummy_col_right_inst, self.dummy_row_top_inst, self.dummy_row_bot_inst] + list(self.replica_col_inst.values())
self.dummy_row_top_inst, self.dummy_row_bot_inst] + list(self.replica_col_inst.values())
else:
supply_insts = self.insts
except AttributeError:
supply_insts = self.insts
for pin_name in ["vdd", "gnd"]: for pin_name in ["vdd", "gnd"]:
for inst in supply_insts: for inst in supply_insts:
pin_list = inst.get_pins(pin_name) pin_list = inst.get_pins(pin_name)

9
compiler/modules/replica_column.py
View File

@ -183,13 +183,8 @@ class replica_column(design.design):
width=self.width, width=self.width,
height=wl_pin.height()) height=wl_pin.height())
# For specific technologies, there is no vdd via within the bitcell. Instead vdd is connect via end caps. # Supplies are only connected in the ends
if end_caps_enabled: for inst in [self.cell_inst[0], self.cell_inst[self.total_size - 1]]:
supply_insts = [self.cell_inst[0], self.cell_inst[self.total_size - 1]]
else:
supply_insts = self.cell_inst.values()
for inst in supply_insts:
for pin_name in ["vdd", "gnd"]: for pin_name in ["vdd", "gnd"]:
if pin_name in inst.mod.pins: if pin_name in inst.mod.pins:
self.copy_layout_pin(inst, pin_name) self.copy_layout_pin(inst, pin_name)