From 1bc0775810685ba142e89a917fb7ae7455303ece Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 29 Jun 2020 10:03:24 -0700 Subject: [PATCH] Only add pins to periphery --- compiler/modules/replica_bitcell_array.py | 14 ++++---------- compiler/modules/replica_column.py | 9 ++------- 2 files changed, 6 insertions(+), 17 deletions(-) diff --git a/compiler/modules/replica_bitcell_array.py b/compiler/modules/replica_bitcell_array.py index 57bb3cf9..09a014ce 100644 --- a/compiler/modules/replica_bitcell_array.py +++ b/compiler/modules/replica_bitcell_array.py @@ -378,16 +378,10 @@ class replica_bitcell_array(design.design): width=pin.width(), height=self.height) - # For specific technologies, there is no vdd via within the bitcell. Instead vdd is connect via end caps. - try: - if cell_properties.bitcell.end_caps_enabled: - supply_insts = [self.dummy_col_left_inst, self.dummy_col_right_inst, - self.dummy_row_top_inst, self.dummy_row_bot_inst] + list(self.replica_col_inst.values()) - else: - supply_insts = self.insts - except AttributeError: - supply_insts = self.insts - + # vdd/gnd are only connected in the perimeter cells + # replica column should only have a vdd/gnd in the dummy cell on top/bottom + supply_insts = [self.dummy_col_left_inst, self.dummy_col_right_inst, + self.dummy_row_top_inst, self.dummy_row_bot_inst] + list(self.replica_col_inst.values()) for pin_name in ["vdd", "gnd"]: for inst in supply_insts: pin_list = inst.get_pins(pin_name) diff --git a/compiler/modules/replica_column.py b/compiler/modules/replica_column.py index 58d35e7f..9cd65e57 100644 --- a/compiler/modules/replica_column.py +++ b/compiler/modules/replica_column.py @@ -183,13 +183,8 @@ class replica_column(design.design): width=self.width, height=wl_pin.height()) - # For specific technologies, there is no vdd via within the bitcell. Instead vdd is connect via end caps. - if end_caps_enabled: - supply_insts = [self.cell_inst[0], self.cell_inst[self.total_size - 1]] - else: - supply_insts = self.cell_inst.values() - - for inst in supply_insts: + # Supplies are only connected in the ends + for inst in [self.cell_inst[0], self.cell_inst[self.total_size - 1]]: for pin_name in ["vdd", "gnd"]: if pin_name in inst.mod.pins: self.copy_layout_pin(inst, pin_name)