From 1afd4341bdf2fc3945eb8ff670e69741322a8fc3 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Fri, 25 Jan 2019 14:22:37 -0800 Subject: [PATCH] Update stage effort of clk_buf_driver --- compiler/modules/control_logic.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index 676927b5..781402de 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -833,7 +833,7 @@ class control_logic(design.design): #Calculate the load on wl_en within the module and add it to external load external_cout = self.sram.get_wl_en_cin() #First stage is the clock buffer - stage_effort_list += self.clkbuf.get_stage_efforts(external_cout, is_clk_bar_rise) + stage_effort_list += self.clk_buf_driver.get_stage_efforts(external_cout, is_clk_bar_rise) last_stage_is_rise = stage_effort_list[-1].is_rise #Then ask the sram for the other path delays (from the bank)