Move delay line module down.

compiler/sram/sram_1bank.py

@@ -527,13 +527,13 @@ class sram_1bank(sram_base):
             # Only input (besides pins) is the replica bitline
             src_pin = self.control_logic_insts[port].get_pin("rbl_bl")
             dest_pin = self.bank_inst.get_pin("rbl_bl_{0}_{0}".format(port))
-            self.add_wire(self.m2_stack[::-1],
+            self.add_wire(self.m3_stack,
                           [src_pin.center(), vector(src_pin.cx(), dest_pin.cy()), dest_pin.rc()])
             self.add_via_stack_center(from_layer=src_pin.layer,
-                                      to_layer="m2",
+                                      to_layer="m4",
                                       offset=src_pin.center())
             self.add_via_stack_center(from_layer=dest_pin.layer,
-                                      to_layer="m2",
+                                      to_layer="m3",
                                       offset=dest_pin.center())
 
     def route_row_addr_dff(self):