From 19ea33d43ddb03e470a5cc3afc9e719eb8bb2cc7 Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 4 May 2021 16:42:42 -0700 Subject: [PATCH] Move delay line module down. --- compiler/modules/control_logic.py | 29 ++++++++++++++++++++--------- compiler/modules/delay_chain.py | 30 ++++++++++++++---------------- compiler/sram/sram_1bank.py | 6 +++--- 3 files changed, 37 insertions(+), 28 deletions(-) diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index eb9a21ed..92b0bcb8 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -346,9 +346,12 @@ class control_logic(design.design): row += 1 self.place_wlen_row(row) row += 1 - self.place_delay(row) + + control_center_y = self.wl_en_inst.uy() + self.m3_pitch + + # Delay chain always gets placed at row 4 + self.place_delay(4) height = self.delay_inst.uy() - control_center_y = self.delay_inst.by() # This offset is used for placement of the control logic in the SRAM level. self.control_logic_center = vector(self.ctrl_dff_inst.rx(), control_center_y) @@ -387,19 +390,22 @@ class control_logic(design.design): def place_delay(self, row): """ Place the replica bitline """ - y_off = row * self.and2.height + 2 * self.m1_pitch + debug.check(row % 2 == 0, "Must place delay chain at even row for supply alignment.") + + # It is flipped on X axis + y_off = (row + self.delay_chain.rows) * self.and2.height # Add the RBL above the rows # Add to the right of the control rows and routing channel - offset = vector(self.delay_chain.width, y_off) - self.delay_inst.place(offset, mirror="MY") + offset = vector(0, y_off) + self.delay_inst.place(offset, mirror="MX") def route_delay(self): - out_pos = self.delay_inst.get_pin("out").bc() + out_pos = self.delay_inst.get_pin("out").center() # Connect to the rail level with the vdd rail - # Use pen since it is in every type of control logic - vdd_ypos = self.p_en_bar_nand_inst.get_pin("vdd").by() + # Use gated clock since it is in every type of control logic + vdd_ypos = self.gated_clk_buf_inst.get_pin("vdd").cy() + self.m1_pitch in_pos = vector(self.input_bus["rbl_bl_delay"].cx(), vdd_ypos) mid1 = vector(out_pos.x, in_pos.y) self.add_wire(self.m1_stack, [out_pos, mid1, in_pos]) @@ -676,7 +682,7 @@ class control_logic(design.design): # Connect the clock rail to the other clock rail # by routing in the supply rail track to avoid channel conflicts in_pos = self.ctrl_dff_inst.get_pin("clk").uc() - mid_pos = in_pos + vector(0, self.and2.height) + mid_pos = vector(in_pos.x, self.gated_clk_buf_inst.get_pin("vdd").cy() - self.m1_pitch) rail_pos = vector(self.input_bus["clk_buf"].cx(), mid_pos.y) self.add_wire(self.m1_stack, [in_pos, mid_pos, rail_pos]) self.add_via_center(layers=self.m1_stack, @@ -794,3 +800,8 @@ class control_logic(design.design): to_layer="m2", offset=out_pos) + def get_left_pins(self, name): + """ + Return the left side supply pins to connect to a vertical stripe. + """ + return(self.cntrl_dff_inst.get_pins(name) + self.delay_inst.get_pins(name)) diff --git a/compiler/modules/delay_chain.py b/compiler/modules/delay_chain.py index d7e9c2d0..4d112343 100644 --- a/compiler/modules/delay_chain.py +++ b/compiler/modules/delay_chain.py @@ -31,6 +31,7 @@ class delay_chain(design.design): # number of inverters including any fanout loads. self.fanout_list = fanout_list + self.rows = len(self.fanout_list) self.create_netlist() if not OPTS.netlist_only: @@ -43,7 +44,7 @@ class delay_chain(design.design): def create_layout(self): # Each stage is a a row - self.height = len(self.fanout_list) * self.inv.height + self.height = self.rows * self.inv.height # The width is determined by the largest fanout plus the driver self.width = (max(self.fanout_list) + 1) * self.inv.width @@ -69,7 +70,7 @@ class delay_chain(design.design): """ Create the inverters and connect them based on the stage list """ self.driver_inst_list = [] self.load_inst_map = {} - for stage_num, fanout_size in zip(range(len(self.fanout_list)), self.fanout_list): + for stage_num, fanout_size in zip(range(self.rows), self.fanout_list): # Add the inverter cur_driver=self.add_inst(name="dinv{}".format(stage_num), mod=self.inv) @@ -77,7 +78,7 @@ class delay_chain(design.design): self.driver_inst_list.append(cur_driver) # Hook up the driver - if stage_num + 1 == len(self.fanout_list): + if stage_num + 1 == self.rows: stageout_name = "out" else: stageout_name = "dout_{}".format(stage_num + 1) @@ -101,7 +102,7 @@ class delay_chain(design.design): def place_inverters(self): """ Place the inverters and connect them based on the stage list """ - for stage_num, fanout_size in zip(range(len(self.fanout_list)), self.fanout_list): + for stage_num, fanout_size in zip(range(self.rows), self.fanout_list): if stage_num % 2: inv_mirror = "MX" inv_offset = vector(0, (stage_num + 1) * self.inv.height) @@ -189,20 +190,17 @@ class delay_chain(design.design): self.add_via_stack_center(from_layer=a_pin.layer, to_layer="m2", offset=a_pin.center()) - self.add_layout_pin(text="in", - layer="m2", - offset=a_pin.ll().scale(1, 0), - height=a_pin.cy()) + self.add_layout_pin_rect_center(text="in", + layer="m2", + offset=a_pin.center()) - # output is A pin of last load inverter + # output is A pin of last load/fanout inverter last_driver_inst = self.driver_inst_list[-1] a_pin = self.load_inst_map[last_driver_inst][-1].get_pin("A") self.add_via_stack_center(from_layer=a_pin.layer, - to_layer="m2", + to_layer="m1", offset=a_pin.center()) - mid_point = vector(a_pin.cx() + 3 * self.m2_width, a_pin.cy()) - self.add_path("m2", [a_pin.center(), mid_point, mid_point.scale(1, 0)]) - self.add_layout_pin_segment_center(text="out", - layer="m2", - start=mid_point, - end=mid_point.scale(1, 0)) + self.add_layout_pin_rect_center(text="out", + layer="m1", + offset=a_pin.center()) + diff --git a/compiler/sram/sram_1bank.py b/compiler/sram/sram_1bank.py index 6bc2cd43..176ce49b 100644 --- a/compiler/sram/sram_1bank.py +++ b/compiler/sram/sram_1bank.py @@ -527,13 +527,13 @@ class sram_1bank(sram_base): # Only input (besides pins) is the replica bitline src_pin = self.control_logic_insts[port].get_pin("rbl_bl") dest_pin = self.bank_inst.get_pin("rbl_bl_{0}_{0}".format(port)) - self.add_wire(self.m2_stack[::-1], + self.add_wire(self.m3_stack, [src_pin.center(), vector(src_pin.cx(), dest_pin.cy()), dest_pin.rc()]) self.add_via_stack_center(from_layer=src_pin.layer, - to_layer="m2", + to_layer="m4", offset=src_pin.center()) self.add_via_stack_center(from_layer=dest_pin.layer, - to_layer="m2", + to_layer="m3", offset=dest_pin.center()) def route_row_addr_dff(self):