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OpenRAM
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Changing control logic names to match naming scheme for multi-port. din[0] to din0[0], s_en to s_en0, addr[0] to addr0[0], etc. Sram level should pass unit tests for single port but will not currently pass for multi-port

This commit is contained in:
Michael Timothy Grimes 2018-08-18 16:51:21 -07:00
parent 0f8da1510e
commit 19ca0d6c2a
4 changed files with 16 additions and 17 deletions
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7
compiler/modules/bank.py
View File

@ -135,7 +135,6 @@ class bank(design.design):
self.add_column_decoder()
def compute_sizes(self):
""" Computes the required sizes to create the bank """
@ -201,7 +200,7 @@ class bank(design.design):
self.precharge_array = [None] * self.total_read
for k in range(self.total_read):
self.precharge_array[k] = self.mod_precharge_array(columns=self.num_cols, BL=self.read_bl_list[k], BR=self.read_br_list[k])
self.precharge_array[k] = self.mod_precharge_array(columns=self.num_cols, bitcell_bl=self.read_bl_list[k], bitcell_br=self.read_br_list[k])
self.add_mod(self.precharge_array[k])
if self.col_addr_size > 0:
@ -575,8 +574,8 @@ class bank(design.design):
for k in range(self.total_read):
for i in range(self.num_cols):
precharge_bl = self.precharge_array_inst[k].get_pin(self.read_bl_list[k]+"[{}]".format(i)).bc()
precharge_br = self.precharge_array_inst[k].get_pin(self.read_br_list[k]+"[{}]".format(i)).bc()
precharge_bl = self.precharge_array_inst[k].get_pin("bl[{}]".format(i)).bc()
precharge_br = self.precharge_array_inst[k].get_pin("br[{}]".format(i)).bc()
bitcell_bl = self.bitcell_array_inst.get_pin(self.read_bl_list[k]+"[{}]".format(i)).uc()
bitcell_br = self.bitcell_array_inst.get_pin(self.read_br_list[k]+"[{}]".format(i)).uc()

10
compiler/modules/control_logic.py
View File

@ -100,7 +100,7 @@ class control_logic(design.design):
# leave space for the bus plus one extra space
self.internal_bus_width = (len(self.internal_bus_list)+1)*self.m2_pitch
# Outputs to the bank
self.output_list = ["s_en", "w_en", "clk_buf_bar", "clk_buf"]
self.output_list = ["s_en0", "w_en0", "clk_buf_bar", "clk_buf"]
self.supply_list = ["vdd", "gnd"]
@ -231,7 +231,7 @@ class control_logic(design.design):
mod=self.inv8,
offset=self.s_en_offset,
mirror=mirror)
self.connect_inst(["pre_s_en_bar", "s_en", "vdd", "gnd"])
self.connect_inst(["pre_s_en_bar", "s_en0", "vdd", "gnd"])
self.row_end_inst.append(self.s_en_inst)
@ -313,7 +313,7 @@ class control_logic(design.design):
mod=self.inv8,
offset=w_en_offset,
mirror=mirror)
self.connect_inst(["pre_w_en_bar", "w_en", "vdd", "gnd"])
self.connect_inst(["pre_w_en_bar", "w_en0", "vdd", "gnd"])
x_off += self.inv8.width
self.row_end_inst.append(self.w_en_inst)
@ -406,7 +406,7 @@ class control_logic(design.design):
self.add_path("metal1",[self.pre_w_en_inst.get_pin("Z").center(), self.pre_w_en_bar_inst.get_pin("A").center()])
self.add_path("metal1",[self.pre_w_en_bar_inst.get_pin("Z").center(), self.w_en_inst.get_pin("A").center()])
self.connect_output(self.w_en_inst, "Z", "w_en")
self.connect_output(self.w_en_inst, "Z", "w_en0")
def route_sen(self):
rbl_out_pos = self.rbl_inst.get_pin("out").bc()
@ -417,7 +417,7 @@ class control_logic(design.design):
self.add_path("metal1",[self.pre_s_en_bar_inst.get_pin("Z").center(), self.s_en_inst.get_pin("A").center()])
self.connect_output(self.s_en_inst, "Z", "s_en")
self.connect_output(self.s_en_inst, "Z", "s_en0")
def route_clk(self):
""" Route the clk and clk_buf_bar signal internally """

8
compiler/sram_1bank.py
View File

@ -75,7 +75,7 @@ class sram_1bank(sram_base):
self.copy_layout_pin(self.control_logic_inst, n)
for i in range(self.word_size):
dout_name = "dout[{}]".format(i)
dout_name = "dout0[{}]".format(i)
self.copy_layout_pin(self.bank_inst, dout_name, dout_name.upper())
# Lower address bits
@ -179,7 +179,7 @@ class sram_1bank(sram_base):
""" Connect the output of the row flops to the bank pins """
for i in range(self.row_addr_size):
flop_name = "dout[{}]".format(i)
bank_name = "addr[{}]".format(i+self.col_addr_size)
bank_name = "addr0[{}]".format(i+self.col_addr_size)
flop_pin = self.row_addr_dff_inst.get_pin(flop_name)
bank_pin = self.bank_inst.get_pin(bank_name)
flop_pos = flop_pin.center()
@ -204,7 +204,7 @@ class sram_1bank(sram_base):
data_dff_map = zip(dff_names, bus_names)
self.connect_horizontal_bus(data_dff_map, self.col_addr_dff_inst, col_addr_bus_offsets)
bank_names = ["addr[{}]".format(x) for x in range(self.col_addr_size)]
bank_names = ["addr0[{}]".format(x) for x in range(self.col_addr_size)]
data_bank_map = zip(bank_names, bus_names)
self.connect_horizontal_bus(data_bank_map, self.bank_inst, col_addr_bus_offsets)
@ -215,7 +215,7 @@ class sram_1bank(sram_base):
offset = self.data_dff_inst.ul() + vector(0, self.m1_pitch)
dff_names = ["dout[{}]".format(x) for x in range(self.word_size)]
bank_names = ["din[{}]".format(x) for x in range(self.word_size)]
bank_names = ["din0[{}]".format(x) for x in range(self.word_size)]
route_map = list(zip(bank_names, dff_names))
dff_pins = {key: self.data_dff_inst.get_pin(key) for key in dff_names }

4
compiler/sram_base.py
View File

@ -150,7 +150,7 @@ class sram_base(design):
""" Add the horizontal and vertical busses """
# Vertical bus
# The order of the control signals on the control bus:
self.control_bus_names = ["clk_buf", "clk_buf_bar", "w_en", "s_en"]
self.control_bus_names = ["clk_buf", "clk_buf_bar", "w_en0", "s_en0"]
self.vert_control_bus_positions = self.create_vertical_bus(layer="metal2",
pitch=self.m2_pitch,
offset=self.vertical_bus_offset,
@ -328,7 +328,7 @@ class sram_base(design):
temp.append("A[{0}]".format(i))
if(self.num_banks > 1):
temp.append("bank_sel[{0}]".format(bank_num))
temp.extend(["s_en", "w_en", "clk_buf_bar","clk_buf" , "vdd", "gnd"])
temp.extend(["s_en0", "w_en0", "clk_buf_bar","clk_buf" , "vdd", "gnd"])
self.connect_inst(temp)
return bank_inst