From 18c8ad265eb9dcc3780287b29a6714ed13c01008 Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 1 Oct 2020 09:55:34 -0700 Subject: [PATCH] Unique name for sram channel routes --- compiler/sram/sram_1bank.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/compiler/sram/sram_1bank.py b/compiler/sram/sram_1bank.py index d35baf23..2dfd8096 100644 --- a/compiler/sram/sram_1bank.py +++ b/compiler/sram/sram_1bank.py @@ -414,7 +414,7 @@ class sram_1bank(sram_base): layer_stack=self.m1_stack, parent=self) if add_routes: - self.add_inst("hc", cr) + self.add_inst(cr.name, cr) self.connect_inst([]) else: self.col_addr_bus_size[port] = cr.height @@ -470,7 +470,7 @@ class sram_1bank(sram_base): layer_stack=layer_stack, parent=self) if add_routes: - self.add_inst("hc", cr) + self.add_inst(cr.name, cr) self.connect_inst([]) else: self.data_bus_size[port] = max(cr.height, self.col_addr_bus_size[port]) + self.data_bus_gap @@ -482,7 +482,7 @@ class sram_1bank(sram_base): layer_stack=layer_stack, parent=self) if add_routes: - self.add_inst("hc", cr) + self.add_inst(cr.name, cr) self.connect_inst([]) else: self.data_bus_size[port] = max(cr.height, self.col_addr_bus_size[port]) + self.data_bus_gap