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Fix bitline names in merge error

This commit is contained in:
Matt Guthaus 2019-07-26 22:03:50 -07:00
parent e750ef22f5
commit 179efe4d04
2 changed files with 17 additions and 18 deletions
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29
compiler/modules/port_data.py
View File

@ -237,8 +237,8 @@ class port_data(design.design):
temp.append("rbl_bl") temp.append("rbl_bl")
temp.append("rbl_br") temp.append("rbl_br")
for bit in range(self.num_cols): for bit in range(self.num_cols):
temp.append("bl_{0}".format(bit)) temp.append(self.bl_names[self.port]+"_{0}".format(bit))
temp.append("br_{0}".format(bit)) temp.append(self.br_names[self.port]+"_{0}".format(bit))
if self.has_rbl() and self.port==1: if self.has_rbl() and self.port==1:
temp.append("rbl_bl") temp.append("rbl_bl")
temp.append("rbl_br") temp.append("rbl_br")
@ -258,17 +258,16 @@ class port_data(design.design):
temp = [] temp = []
for col in range(self.num_cols): for col in range(self.num_cols):
temp.append("bl_{0}".format(col)) temp.append(self.bl_names[self.port]+"_{0}".format(col))
temp.append("br_{0}".format(col)) temp.append(self.br_names[self.port]+"_{0}".format(col))
for word in range(self.words_per_row): for word in range(self.words_per_row):
temp.append("sel_{}".format(word)) temp.append("sel_{}".format(word))
for bit in range(self.word_size): for bit in range(self.word_size):
temp.append("bl_out_{0}".format(bit)) temp.append(self.bl_names[self.port]+"_out_{0}".format(bit))
temp.append("br_out_{0}".format(bit)) temp.append(self.br_names[self.port]+"_out_{0}".format(bit))
temp.append("gnd") temp.append("gnd")
self.connect_inst(temp) self.connect_inst(temp)
def place_column_mux_array(self, offset): def place_column_mux_array(self, offset):
""" Placing Column Mux when words_per_row > 1 . """ """ Placing Column Mux when words_per_row > 1 . """
@ -287,12 +286,12 @@ class port_data(design.design):
for bit in range(self.word_size): for bit in range(self.word_size):
temp.append("dout_{}".format(bit)) temp.append("dout_{}".format(bit))
if self.words_per_row == 1: if self.words_per_row == 1:
temp.append("bl_{0}".format(bit)) temp.append(self.bl_names[self.port]+"_{0}".format(bit))
temp.append("br_{0}".format(bit)) temp.append(self.br_names[self.port]+"_{0}".format(bit))
else: else:
temp.append("bl_out_{0}".format(bit)) temp.append(self.bl_names[self.port]+"_out_{0}".format(bit))
temp.append("br_out_{0}".format(bit)) temp.append(self.br_names[self.port]+"_out_{0}".format(bit))
temp.extend(["s_en", "vdd", "gnd"]) temp.extend(["s_en", "vdd", "gnd"])
self.connect_inst(temp) self.connect_inst(temp)
@ -312,9 +311,9 @@ class port_data(design.design):
temp.append("din_{}".format(bit)) temp.append("din_{}".format(bit))
for bit in range(self.word_size): for bit in range(self.word_size):
if (self.words_per_row == 1): if (self.words_per_row == 1):
temp.append("bl_{0}".format(bit)) temp.append(self.bl_names[self.port]+"_{0}".format(bit))
temp.append("br_{0}".format(bit)) temp.append(self.br_names[self.port]+"_{0}".format(bit))
else: else:
temp.append(self.bl_names[self.port]+"_out_{0}".format(bit)) temp.append(self.bl_names[self.port]+"_out_{0}".format(bit))
temp.append(self.br_names[self.port]+"_out_{0}".format(bit)) temp.append(self.br_names[self.port]+"_out_{0}".format(bit))

6
compiler/tests/16_control_logic_test.py
View File

@ -23,15 +23,15 @@ class control_logic_test(openram_test):
import tech import tech
debug.info(1, "Testing sample for control_logic_rw") debug.info(1, "Testing sample for control_logic_rw")
a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=32, write_size=32) a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=32)
self.local_check(a) self.local_check(a)
debug.info(1, "Testing sample for control_logic_r") debug.info(1, "Testing sample for control_logic_r")
a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=32, write_size=32, port_type="r") a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=32, port_type="r")
self.local_check(a) self.local_check(a)
debug.info(1, "Testing sample for control_logic_w") debug.info(1, "Testing sample for control_logic_w")
a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=32, write_size=32, port_type="w") a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=32, port_type="w")
self.local_check(a) self.local_check(a)
# run the test from the command line # run the test from the command line