diff --git a/compiler/modules/port_data.py b/compiler/modules/port_data.py
index cee79c47..ac023eb0 100644
--- a/compiler/modules/port_data.py
+++ b/compiler/modules/port_data.py
@@ -237,8 +237,8 @@ class port_data(design.design):
             temp.append("rbl_bl")
             temp.append("rbl_br")
         for bit in range(self.num_cols):
-            temp.append("bl_{0}".format(bit))
-            temp.append("br_{0}".format(bit))
+            temp.append(self.bl_names[self.port]+"_{0}".format(bit))
+            temp.append(self.br_names[self.port]+"_{0}".format(bit))
         if self.has_rbl() and self.port==1:
             temp.append("rbl_bl")
             temp.append("rbl_br")
@@ -258,17 +258,16 @@ class port_data(design.design):
 
         temp = []
         for col in range(self.num_cols):
-            temp.append("bl_{0}".format(col))
-            temp.append("br_{0}".format(col))
+            temp.append(self.bl_names[self.port]+"_{0}".format(col))
+            temp.append(self.br_names[self.port]+"_{0}".format(col))
         for word in range(self.words_per_row):
             temp.append("sel_{}".format(word))
         for bit in range(self.word_size):
-            temp.append("bl_out_{0}".format(bit))
-            temp.append("br_out_{0}".format(bit))
+            temp.append(self.bl_names[self.port]+"_out_{0}".format(bit))
+            temp.append(self.br_names[self.port]+"_out_{0}".format(bit))
         temp.append("gnd")
         self.connect_inst(temp)
 
-
             
     def place_column_mux_array(self, offset):
         """ Placing Column Mux when words_per_row > 1 . """
@@ -287,12 +286,12 @@ class port_data(design.design):
         for bit in range(self.word_size):
             temp.append("dout_{}".format(bit))
             if self.words_per_row == 1:
-                temp.append("bl_{0}".format(bit))
-                temp.append("br_{0}".format(bit))
+                temp.append(self.bl_names[self.port]+"_{0}".format(bit))
+                temp.append(self.br_names[self.port]+"_{0}".format(bit))
             else:
-                temp.append("bl_out_{0}".format(bit))
-                temp.append("br_out_{0}".format(bit))
-                    
+                temp.append(self.bl_names[self.port]+"_out_{0}".format(bit))
+                temp.append(self.br_names[self.port]+"_out_{0}".format(bit))
+               
         temp.extend(["s_en", "vdd", "gnd"])
         self.connect_inst(temp)
 
@@ -312,9 +311,9 @@ class port_data(design.design):
             temp.append("din_{}".format(bit))
 
         for bit in range(self.word_size):            
-            if (self.words_per_row == 1):            
-                temp.append("bl_{0}".format(bit))
-                temp.append("br_{0}".format(bit))
+            if (self.words_per_row == 1):
+                temp.append(self.bl_names[self.port]+"_{0}".format(bit))
+                temp.append(self.br_names[self.port]+"_{0}".format(bit))
             else:
                 temp.append(self.bl_names[self.port]+"_out_{0}".format(bit))
                 temp.append(self.br_names[self.port]+"_out_{0}".format(bit))
diff --git a/compiler/tests/16_control_logic_test.py b/compiler/tests/16_control_logic_test.py
index f8fa3061..92d5c94b 100755
--- a/compiler/tests/16_control_logic_test.py
+++ b/compiler/tests/16_control_logic_test.py
@@ -23,15 +23,15 @@ class control_logic_test(openram_test):
         import tech
 
         debug.info(1, "Testing sample for control_logic_rw")
-        a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=32, write_size=32)
+        a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=32)
         self.local_check(a)
 
         debug.info(1, "Testing sample for control_logic_r")
-        a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=32, write_size=32, port_type="r")
+        a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=32, port_type="r")
         self.local_check(a)
 
         debug.info(1, "Testing sample for control_logic_w")
-        a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=32, write_size=32, port_type="w")
+        a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=32, port_type="w")
         self.local_check(a)
         
 # run the test from the command line