luke/OpenRAM
1
0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-09-07 03:20:39 +02:00
Code Issues Packages Projects Releases Wiki Activity

Fix bitline names in merge error

Browse Source
This commit is contained in:
Matt Guthaus
2019-07-26 22:03:50 -07:00
parent e750ef22f5
commit 179efe4d04
2 changed files with 17 additions and 18 deletions
Download Patch File Download Diff File Expand all files Collapse all files
compiler/tests/16_control_logic_test.py
+3 -3
View File
@@ -23,15 +23,15 @@ class control_logic_test(openram_test):
import tech
debug.info(1, "Testing sample for control_logic_rw")
a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=32, write_size=32)
a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=32)
self.local_check(a)
debug.info(1, "Testing sample for control_logic_r")
a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=32, write_size=32, port_type="r")
a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=32, port_type="r")
self.local_check(a)
debug.info(1, "Testing sample for control_logic_w")
a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=32, write_size=32, port_type="w")
a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=32, port_type="w")
self.local_check(a)
# run the test from the command line