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Fix bitline names in merge error

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This commit is contained in:
Matt Guthaus
2019-07-26 22:03:50 -07:00
parent e750ef22f5
commit 179efe4d04
2 changed files with 17 additions and 18 deletions
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compiler/modules/port_data.py
+14 -15
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@@ -237,8 +237,8 @@ class port_data(design.design):
temp.append("rbl_bl")
temp.append("rbl_br")
for bit in range(self.num_cols):
temp.append("bl_{0}".format(bit))
temp.append("br_{0}".format(bit))
temp.append(self.bl_names[self.port]+"_{0}".format(bit))
temp.append(self.br_names[self.port]+"_{0}".format(bit))
if self.has_rbl() and self.port==1:
temp.append("rbl_bl")
temp.append("rbl_br")
@@ -258,17 +258,16 @@ class port_data(design.design):
temp = []
for col in range(self.num_cols):
temp.append("bl_{0}".format(col))
temp.append("br_{0}".format(col))
temp.append(self.bl_names[self.port]+"_{0}".format(col))
temp.append(self.br_names[self.port]+"_{0}".format(col))
for word in range(self.words_per_row):
temp.append("sel_{}".format(word))
for bit in range(self.word_size):
temp.append("bl_out_{0}".format(bit))
temp.append("br_out_{0}".format(bit))
temp.append(self.bl_names[self.port]+"_out_{0}".format(bit))
temp.append(self.br_names[self.port]+"_out_{0}".format(bit))
temp.append("gnd")
self.connect_inst(temp)
def place_column_mux_array(self, offset):
""" Placing Column Mux when words_per_row > 1 . """
@@ -287,12 +286,12 @@ class port_data(design.design):
for bit in range(self.word_size):
temp.append("dout_{}".format(bit))
if self.words_per_row == 1:
temp.append("bl_{0}".format(bit))
temp.append("br_{0}".format(bit))
temp.append(self.bl_names[self.port]+"_{0}".format(bit))
temp.append(self.br_names[self.port]+"_{0}".format(bit))
else:
temp.append("bl_out_{0}".format(bit))
temp.append("br_out_{0}".format(bit))
temp.append(self.bl_names[self.port]+"_out_{0}".format(bit))
temp.append(self.br_names[self.port]+"_out_{0}".format(bit))
temp.extend(["s_en", "vdd", "gnd"])
self.connect_inst(temp)
@@ -312,9 +311,9 @@ class port_data(design.design):
temp.append("din_{}".format(bit))
for bit in range(self.word_size):
if (self.words_per_row == 1):
temp.append("bl_{0}".format(bit))
temp.append("br_{0}".format(bit))
if (self.words_per_row == 1):
temp.append(self.bl_names[self.port]+"_{0}".format(bit))
temp.append(self.br_names[self.port]+"_{0}".format(bit))
else:
temp.append(self.bl_names[self.port]+"_out_{0}".format(bit))
temp.append(self.br_names[self.port]+"_out_{0}".format(bit))