Clean up time statements in openram output

compiler/characterizer/lib.py

@@ -12,9 +12,9 @@ from globals import OPTS
 class lib:
     """ lib file generation."""
     
-    def __init__(self, libname, sram, spfile, use_model=OPTS.analytical_delay):
+    def __init__(self, libname, sram, sp_file, use_model=OPTS.analytical_delay):
         self.sram = sram
-        self.sp_file = spfile        
+        self.sp_file = sp_file        
         self.use_model = use_model
         self.name = sram.name
         self.num_words = sram.num_words

compiler/globals.py

@@ -281,12 +281,12 @@ def import_tech():
         sys.exit(1)
 
 def print_time(name, now_time, last_time=None):
+    """ Print a statement about the time delta. """
     if last_time:
         time = round((now_time-last_time).total_seconds(),1)
     else:
         time = now_time
     print("** {0}: {1} seconds".format(name,time))
-    return now_time
 
 
 def report_status():

compiler/openram.py

@@ -32,18 +32,16 @@ import sram
 
 # Keep track of running stats
 start_time = datetime.datetime.now()
-last_time = start_time
+print_time("Start",start_time)
-print_time("Start",last_time)
 
 # import SRAM test generation
 s = sram.sram(word_size=OPTS.word_size,
               num_words=OPTS.num_words,
               num_banks=OPTS.num_banks,
               name=OPTS.output_name)
-last_time=print_time("SRAM creation", datetime.datetime.now(), last_time)
 
 # Output the files for the resulting SRAM
-s.save_output(last_time)
+s.save_output()
 
 # Delete temp files etc.
 end_openram()

compiler/sram.py

@@ -45,6 +45,7 @@ class sram(design.design):
 
         debug.info(2, "create sram of size {0} with {1} num of words".format(self.word_size, 
                                                                              self.num_words))
+        start_time = datetime.datetime.now()
 
         design.design.__init__(self, name)
 
@@ -74,6 +75,9 @@ class sram(design.design):
         
         self.DRC_LVS(final_verification=True)
 
+        print_time("SRAM creation", datetime.datetime.now(), start_time)
+
+
     def compute_sizes(self):
         """  Computes the organization of the memory using bitcell size by trying to make it square."""
 
@@ -1011,21 +1015,29 @@ class sram(design.design):
         return self.bank.analytical_delay(slew,load)
 
 
-    def save_output(self, last_time):
+    def save_output(self):
         """ Save all the output files while reporting time to do it as well. """
 
+        # Save the spice file
+        start_time = datetime.datetime.now()
         spname = OPTS.output_path + self.name + ".sp"
         print("SP: Writing to {0}".format(spname))
         self.sp_write(spname)
-        last_time=print_time("Spice writing", datetime.datetime.now(), last_time)
+        print_time("Spice writing", datetime.datetime.now(), start_time)
 
-        # Output the extracted design
+        # Save the extracted spice file
-        sram_file = spname
         if OPTS.use_pex:
-            sram_file = OPTS.output_path + "temp_pex.sp"
+            start_time = datetime.datetime.now()
-            verify.run_pex(self.name, gdsname, spname, output=sram_file)
+            # Output the extracted design if requested
+            sp_file = OPTS.output_path + "temp_pex.sp"
+            verify.run_pex(self.name, gdsname, spname, output=sp_file)
+            print_time("Extraction", datetime.datetime.now(), start_time)
+        else:
+            # Use generated spice file for characterization
+            sp_file = spname
         
         # Characterize the design
+        start_time = datetime.datetime.now()        
         from characterizer import lib
         libname = OPTS.output_path + self.name + ".lib"
         print("LIB: Writing to {0}".format(libname))
@@ -1036,23 +1048,26 @@ class sram(design.design):
                 print("Performing simulation-based characterization with {}".format(OPTS.spice_name))
             if OPTS.trim_netlist:
                 print("Trimming netlist to speed up characterization.")
-        lib.lib(libname,self,sram_file)
+        lib.lib(libname=libname,sram=self,sp_file=sp_file)
-        last_time=print_time("Characterization", datetime.datetime.now(), last_time)
+        print_time("Characterization", datetime.datetime.now(), start_time)
 
         # Write the layout
+        start_time = datetime.datetime.now()
         gdsname = OPTS.output_path + self.name + ".gds"
         print("GDS: Writing to {0}".format(gdsname))
         self.gds_write(gdsname)
-        last_time=print_time("GDS", datetime.datetime.now(), last_time)
+        print_time("GDS", datetime.datetime.now(), start_time)
 
         # Create a LEF physical model
+        start_time = datetime.datetime.now()
         lefname = OPTS.output_path + self.name + ".lef"
         print("LEF: Writing to {0}".format(lefname))
         self.lef_write(lefname)
-        last_time=print_time("LEF", datetime.datetime.now(), last_time)
+        print_time("LEF", datetime.datetime.now(), start_time)
 
         # Write a verilog model
+        start_time = datetime.datetime.now()
         vname = OPTS.output_path + self.name + ".v"
         print("Verilog: Writing to {0}".format(vname))
         self.verilog_write(vname)
-        last_time=print_time("Verilog", datetime.datetime.now(), last_time)
+        print_time("Verilog", datetime.datetime.now(), start_time)