Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev

compiler/modules/bank.py

@@ -74,7 +74,6 @@ class bank(design.design):
         self.bank_array_ll = self.offset_all_coordinates().scale(-1, -1)
         self.bank_array_ur = self.bitcell_array_inst.ur()
         self.bank_array_ul = self.bitcell_array_inst.ul()
-
         self.DRC_LVS()
 
     def add_pins(self):
@@ -1050,7 +1049,7 @@ class bank(design.design):
                                                                                                 inp_is_rise)
         
         return stage_effort_list
-        
+
     def get_wl_en_cin(self):
         """Get the relative capacitance of all the clk connections in the bank"""
         # wl_en only used in the wordline driver.

compiler/modules/control_logic.py

@@ -869,7 +869,6 @@ class control_logic(design.design):
                            offset=pin.ll(),
                            height=pin.height(),
                            width=pin.width())
-
     def get_delays_to_wl(self):
         """Get the delay (in delay units) of the clk to a wordline in the bitcell array"""
         debug.check(self.sram.all_mods_except_control_done, "Cannot calculate sense amp enable delay unless all module have been added.")