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OpenRAM
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When determining bitline names, added a technology check for sky130.

This commit is contained in:
Hunter Nichols 2021-06-16 17:04:02 -07:00
parent e775f7a355
commit 16e658726e
4 changed files with 8 additions and 6 deletions
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2
compiler/base/hierarchy_spice.py
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@ -32,7 +32,6 @@ class spice():
# This gets set in both spice and layout so either can be called first. # This gets set in both spice and layout so either can be called first.
self.name = name self.name = name
self.cell_name = cell_name self.cell_name = cell_name
self.sp_file = OPTS.openram_tech + "sp_lib/" + cell_name + ".sp" self.sp_file = OPTS.openram_tech + "sp_lib/" + cell_name + ".sp"
# If we have a separate lvs directory, then all the lvs files # If we have a separate lvs directory, then all the lvs files
@ -570,6 +569,7 @@ class spice():
net = net.lower() net = net.lower()
int_net = self.name_dict[net]['int_net'] int_net = self.name_dict[net]['int_net']
int_mod = self.name_dict[net]['mod'] int_mod = self.name_dict[net]['mod']
if int_mod.is_net_alias(int_net, alias, alias_mod, exclusion_set): if int_mod.is_net_alias(int_net, alias, alias_mod, exclusion_set):
aliases.append(net) aliases.append(net)
return aliases return aliases

3
compiler/bitcells/bitcell_base.py
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@ -26,7 +26,6 @@ class bitcell_base(design.design):
self.nets_match = self.do_nets_exist(prop.storage_nets) self.nets_match = self.do_nets_exist(prop.storage_nets)
self.mirror = prop.mirror self.mirror = prop.mirror
self.end_caps = prop.end_caps self.end_caps = prop.end_caps
def get_stage_effort(self, load): def get_stage_effort(self, load):
parasitic_delay = 1 parasitic_delay = 1
# This accounts for bitline being drained # This accounts for bitline being drained
@ -84,7 +83,7 @@ class bitcell_base(design.design):
return self.storage_nets return self.storage_nets
else: else:
fmt_str = "Storage nodes={} not found in spice file." fmt_str = "Storage nodes={} not found in spice file."
debug.info(1, fmt_str.format(self.storage_nets)) debug.warning(fmt_str.format(self.storage_nets))
return None return None
def get_storage_net_offset(self): def get_storage_net_offset(self):

6
compiler/characterizer/simulation.py
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@ -576,7 +576,11 @@ class simulation():
""" """
Gets the signal name associated with the bitlines in the bank. Gets the signal name associated with the bitlines in the bank.
""" """
cell_mod = factory.create(module_type=OPTS.bitcell) # FIXME: change to a solution that does not depend on the technology
if OPTS.tech_name == 'sky130':
cell_mod = factory.create(module_type=OPTS.bitcell, version="opt1")
else:
cell_mod = factory.create(module_type=OPTS.bitcell)
cell_bl = cell_mod.get_bl_name(port) cell_bl = cell_mod.get_bl_name(port)
cell_br = cell_mod.get_br_name(port) cell_br = cell_mod.get_br_name(port)

3
compiler/modules/replica_column.py
View File

@ -238,5 +238,4 @@ class replica_column(bitcell_base_array):
for row, cell in enumerate(self.cell_inst): for row, cell in enumerate(self.cell_inst):
if row != self.replica_bit: if row != self.replica_bit:
self.graph_inst_exclude.add(cell) self.graph_inst_exclude.add(cell)