From 16e658726e68183d4b25a898fab16e7486dbadfe Mon Sep 17 00:00:00 2001
From: Hunter Nichols <hznichol@ucsc.edu>
Date: Wed, 16 Jun 2021 17:04:02 -0700
Subject: [PATCH] When determining bitline names, added a technology check for
 sky130.

---
 compiler/base/hierarchy_spice.py     | 2 +-
 compiler/bitcells/bitcell_base.py    | 3 +--
 compiler/characterizer/simulation.py | 6 +++++-
 compiler/modules/replica_column.py   | 3 +--
 4 files changed, 8 insertions(+), 6 deletions(-)

diff --git a/compiler/base/hierarchy_spice.py b/compiler/base/hierarchy_spice.py
index 2f2d3ec9..eca98eaf 100644
--- a/compiler/base/hierarchy_spice.py
+++ b/compiler/base/hierarchy_spice.py
@@ -32,7 +32,6 @@ class spice():
         # This gets set in both spice and layout so either can be called first.
         self.name = name
         self.cell_name = cell_name
-
         self.sp_file = OPTS.openram_tech + "sp_lib/" + cell_name + ".sp"
 
         # If we have a separate lvs directory, then all the lvs files
@@ -570,6 +569,7 @@ class spice():
             net = net.lower()
             int_net = self.name_dict[net]['int_net']
             int_mod = self.name_dict[net]['mod']
+
             if int_mod.is_net_alias(int_net, alias, alias_mod, exclusion_set):
                 aliases.append(net)
         return aliases
diff --git a/compiler/bitcells/bitcell_base.py b/compiler/bitcells/bitcell_base.py
index 5112642e..1161fec8 100644
--- a/compiler/bitcells/bitcell_base.py
+++ b/compiler/bitcells/bitcell_base.py
@@ -26,7 +26,6 @@ class bitcell_base(design.design):
             self.nets_match = self.do_nets_exist(prop.storage_nets)
             self.mirror = prop.mirror
             self.end_caps = prop.end_caps
-          
     def get_stage_effort(self, load):
         parasitic_delay = 1
         # This accounts for bitline being drained
@@ -84,7 +83,7 @@ class bitcell_base(design.design):
             return self.storage_nets
         else:
             fmt_str = "Storage nodes={} not found in spice file."
-            debug.info(1, fmt_str.format(self.storage_nets))
+            debug.warning(fmt_str.format(self.storage_nets))
             return None
 
     def get_storage_net_offset(self):
diff --git a/compiler/characterizer/simulation.py b/compiler/characterizer/simulation.py
index e985e951..846161e5 100644
--- a/compiler/characterizer/simulation.py
+++ b/compiler/characterizer/simulation.py
@@ -576,7 +576,11 @@ class simulation():
         """
         Gets the signal name associated with the bitlines in the bank.
         """
-        cell_mod = factory.create(module_type=OPTS.bitcell)
+        # FIXME: change to a solution that does not depend on the technology
+        if OPTS.tech_name == 'sky130':
+            cell_mod = factory.create(module_type=OPTS.bitcell, version="opt1")
+        else:
+            cell_mod = factory.create(module_type=OPTS.bitcell)
         cell_bl = cell_mod.get_bl_name(port)
         cell_br = cell_mod.get_br_name(port)
 
diff --git a/compiler/modules/replica_column.py b/compiler/modules/replica_column.py
index b890566a..d237bcc8 100644
--- a/compiler/modules/replica_column.py
+++ b/compiler/modules/replica_column.py
@@ -238,5 +238,4 @@ class replica_column(bitcell_base_array):
         for row, cell in enumerate(self.cell_inst):
             if row != self.replica_bit:
                 self.graph_inst_exclude.add(cell)
-
-
+