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Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev

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mrg
2020-09-28 15:51:35 -07:00
parent 392afd4d4b 88731ccd8e
commit 159c04a25d
9 changed files with 20 additions and 11 deletions
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compiler/modules/bank.py
+1 -1
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@@ -27,7 +27,7 @@ class bank(design.design):
self.sram_config = sram_config
sram_config.set_local_config(self)
if self.write_size:
self.num_wmasks = int(self.word_size / self.write_size)
self.num_wmasks = int(ceil(self.word_size / self.write_size))
else:
self.num_wmasks = 0
compiler/modules/port_data.py
+2 -1
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@@ -6,6 +6,7 @@
from tech import drc
import debug
import design
import math
from sram_factory import factory
from collections import namedtuple
from vector import vector
@@ -23,7 +24,7 @@ class port_data(design.design):
sram_config.set_local_config(self)
self.port = port
if self.write_size is not None:
self.num_wmasks = int(self.word_size / self.write_size)
self.num_wmasks = int(math.ceil(self.word_size / self.write_size))
else:
self.num_wmasks = 0
compiler/modules/write_driver_array.py
+2 -1
View File
@@ -7,6 +7,7 @@
#
import design
import debug
import math
from tech import drc
from sram_factory import factory
from vector import vector
@@ -39,7 +40,7 @@ class write_driver_array(design.design):
self.num_spare_cols = num_spare_cols
if self.write_size:
self.num_wmasks = int(self.word_size / self.write_size)
self.num_wmasks = int(math.ceil(self.word_size / self.write_size))
self.create_netlist()
if not OPTS.netlist_only:
compiler/modules/write_mask_and_array.py
+2 -1
View File
@@ -7,6 +7,7 @@
#
import design
import debug
import math
from sram_factory import factory
from vector import vector
from globals import OPTS
@@ -31,7 +32,7 @@ class write_mask_and_array(design.design):
self.offsets = offsets
self.column_offset = column_offset
self.words_per_row = int(columns / word_size)
self.num_wmasks = int(word_size / write_size)
self.num_wmasks = int(math.ceil(word_size / write_size))
self.create_netlist()
if not OPTS.netlist_only: