diff --git a/compiler/base/verilog.py b/compiler/base/verilog.py index 04344738..aadf602c 100644 --- a/compiler/base/verilog.py +++ b/compiler/base/verilog.py @@ -6,6 +6,7 @@ # All rights reserved. # import debug +import math class verilog: """ @@ -53,7 +54,7 @@ class verilog: self.vf.write("\n );\n\n") if self.write_size: - self.num_wmasks = int(self.word_size/self.write_size) + self.num_wmasks = int(math.ceil(self.word_size / self.write_size)) self.vf.write(" parameter NUM_WMASKS = {0} ;\n".format(self.num_wmasks)) self.vf.write(" parameter DATA_WIDTH = {0} ;\n".format(self.word_size)) self.vf.write(" parameter ADDR_WIDTH = {0} ;\n".format(self.addr_size)) @@ -189,9 +190,13 @@ class verilog: self.vf.write(" if (!csb{0}_reg)\n".format(port)) if self.write_size: + remainder_bits = self.word_size % self.write_size for mask in range(0,self.num_wmasks): lower = mask * self.write_size - upper = lower + self.write_size-1 + if (remainder_bits and mask == self.num_wmasks - 1): + upper = lower + remainder_bits - 1 + else: + upper = lower + self.write_size - 1 self.vf.write(" if (wmask{0}_reg[{1}])\n".format(port,mask)) self.vf.write(" mem[addr{0}_reg][{1}:{2}] = din{0}_reg[{1}:{2}];\n".format(port,upper,lower)) self.vf.write(" end\n") diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py index f04965e5..f81e8fa8 100644 --- a/compiler/characterizer/delay.py +++ b/compiler/characterizer/delay.py @@ -47,7 +47,7 @@ class delay(simulation): self.targ_write_ports = [] self.period = 0 if self.write_size: - self.num_wmasks = int(self.word_size / self.write_size) + self.num_wmasks = int(math.ceil(self.word_size / self.write_size)) else: self.num_wmasks = 0 self.set_load_slew(0,0) diff --git a/compiler/characterizer/functional.py b/compiler/characterizer/functional.py index 395c612b..bb9f990d 100644 --- a/compiler/characterizer/functional.py +++ b/compiler/characterizer/functional.py @@ -8,6 +8,7 @@ import collections import debug import random +import math from .stimuli import * from .charutils import * from globals import OPTS @@ -31,7 +32,7 @@ class functional(simulation): random.seed(12345) if self.write_size: - self.num_wmasks = int(self.word_size / self.write_size) + self.num_wmasks = int(math.ceil(self.word_size / self.write_size)) else: self.num_wmasks = 0 diff --git a/compiler/characterizer/simulation.py b/compiler/characterizer/simulation.py index b73af4f6..b6774e99 100644 --- a/compiler/characterizer/simulation.py +++ b/compiler/characterizer/simulation.py @@ -39,7 +39,7 @@ class simulation(): self.write_ports = self.sram.write_ports self.words_per_row = self.sram.words_per_row if self.write_size: - self.num_wmasks = int(self.word_size/self.write_size) + self.num_wmasks = int(math.ceil(self.word_size/self.write_size)) else: self.num_wmasks = 0 diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index 51f6c19b..7bddc60a 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -27,7 +27,7 @@ class bank(design.design): self.sram_config = sram_config sram_config.set_local_config(self) if self.write_size: - self.num_wmasks = int(self.word_size / self.write_size) + self.num_wmasks = int(ceil(self.word_size / self.write_size)) else: self.num_wmasks = 0 diff --git a/compiler/modules/port_data.py b/compiler/modules/port_data.py index 0571201d..c013bc4a 100644 --- a/compiler/modules/port_data.py +++ b/compiler/modules/port_data.py @@ -6,6 +6,7 @@ from tech import drc import debug import design +import math from sram_factory import factory from collections import namedtuple from vector import vector @@ -23,7 +24,7 @@ class port_data(design.design): sram_config.set_local_config(self) self.port = port if self.write_size is not None: - self.num_wmasks = int(self.word_size / self.write_size) + self.num_wmasks = int(math.ceil(self.word_size / self.write_size)) else: self.num_wmasks = 0 diff --git a/compiler/modules/write_driver_array.py b/compiler/modules/write_driver_array.py index 568b192d..a2458f42 100644 --- a/compiler/modules/write_driver_array.py +++ b/compiler/modules/write_driver_array.py @@ -7,6 +7,7 @@ # import design import debug +import math from tech import drc from sram_factory import factory from vector import vector @@ -39,7 +40,7 @@ class write_driver_array(design.design): self.num_spare_cols = num_spare_cols if self.write_size: - self.num_wmasks = int(self.word_size / self.write_size) + self.num_wmasks = int(math.ceil(self.word_size / self.write_size)) self.create_netlist() if not OPTS.netlist_only: diff --git a/compiler/modules/write_mask_and_array.py b/compiler/modules/write_mask_and_array.py index e2048d3d..94446755 100644 --- a/compiler/modules/write_mask_and_array.py +++ b/compiler/modules/write_mask_and_array.py @@ -7,6 +7,7 @@ # import design import debug +import math from sram_factory import factory from vector import vector from globals import OPTS @@ -31,7 +32,7 @@ class write_mask_and_array(design.design): self.offsets = offsets self.column_offset = column_offset self.words_per_row = int(columns / word_size) - self.num_wmasks = int(word_size / write_size) + self.num_wmasks = int(math.ceil(word_size / write_size)) self.create_netlist() if not OPTS.netlist_only: diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py index c9eb4ea1..55e2de49 100644 --- a/compiler/sram/sram_base.py +++ b/compiler/sram/sram_base.py @@ -7,7 +7,7 @@ # import datetime import debug -from math import log +from math import log, ceil from importlib import reload from vector import vector from globals import OPTS, print_time @@ -36,7 +36,7 @@ class sram_base(design, verilog, lef): self.bank_insts = [] if self.write_size: - self.num_wmasks = int(self.word_size / self.write_size) + self.num_wmasks = int(ceil(self.word_size / self.write_size)) else: self.num_wmasks = 0