mirror of https://github.com/VLSIDA/OpenRAM.git
Flip freepdk45 flop, dff_buf route layer change
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157926960b
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@ -7,7 +7,7 @@
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#
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#
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import debug
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import debug
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import design
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import design
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from tech import parameter
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from tech import parameter, layer
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from tech import cell_properties as props
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from tech import cell_properties as props
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from vector import vector
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from vector import vector
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from globals import OPTS
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from globals import OPTS
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@ -52,7 +52,6 @@ class dff_buf(design.design):
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def create_layout(self):
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def create_layout(self):
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self.place_instances()
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self.place_instances()
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self.width = self.inv2_inst.rx()
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self.width = self.inv2_inst.rx()
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self.height = self.dff.height
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self.height = self.dff.height
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self.route_wires()
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self.route_wires()
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self.add_layout_pins()
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self.add_layout_pins()
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@ -125,34 +124,32 @@ class dff_buf(design.design):
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self.inv2_inst.place(vector(self.inv1_inst.rx(), 0))
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self.inv2_inst.place(vector(self.inv1_inst.rx(), 0))
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def route_wires(self):
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def route_wires(self):
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if "li" in layer:
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self.route_layer = "li"
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else:
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self.route_layer = "m1"
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# Route dff q to inv1 a
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# Route dff q to inv1 a
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q_pin = self.dff_inst.get_pin("Q")
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q_pin = self.dff_inst.get_pin("Q")
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a1_pin = self.inv1_inst.get_pin("A")
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a1_pin = self.inv1_inst.get_pin("A")
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mid_x_offset = 0.5 * (a1_pin.cx() + q_pin.cx())
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mid1 = vector(a1_pin.cx(), q_pin.cy())
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mid1 = vector(mid_x_offset, q_pin.cy())
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self.add_path(q_pin.layer, [q_pin.center(), mid1, a1_pin.center()])
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mid2 = vector(mid_x_offset, a1_pin.cy())
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self.add_via_stack_center(from_layer=a1_pin.layer,
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self.add_path("m3", [q_pin.center(), mid1, mid2, a1_pin.center()])
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to_layer=q_pin.layer,
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self.add_via_center(layers=self.m2_stack,
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offset=a1_pin.center())
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offset=q_pin.center())
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self.add_via_center(layers=self.m2_stack,
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offset=a1_pin.center())
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self.add_via_center(layers=self.m1_stack,
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offset=a1_pin.center())
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# Route inv1 z to inv2 a
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# Route inv1 z to inv2 a
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z1_pin = self.inv1_inst.get_pin("Z")
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z1_pin = self.inv1_inst.get_pin("Z")
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a2_pin = self.inv2_inst.get_pin("A")
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a2_pin = self.inv2_inst.get_pin("A")
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mid_x_offset = 0.5 * (z1_pin.cx() + a2_pin.cx())
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self.mid_qb_pos = vector(0.5 * (z1_pin.cx() + a2_pin.cx()), z1_pin.cy())
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self.mid_qb_pos = vector(mid_x_offset, z1_pin.cy())
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self.add_zjog(z1_pin.layer, z1_pin.center(), a2_pin.center())
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mid2 = vector(mid_x_offset, a2_pin.cy())
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self.add_path("m1", [z1_pin.center(), self.mid_qb_pos, mid2, a2_pin.center()])
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def add_layout_pins(self):
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def add_layout_pins(self):
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# Continous vdd rail along with label.
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# Continous vdd rail along with label.
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vdd_pin=self.dff_inst.get_pin("vdd")
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vdd_pin=self.dff_inst.get_pin("vdd")
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self.add_layout_pin(text="vdd",
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self.add_layout_pin(text="vdd",
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layer="m1",
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layer=vdd_pin.layer,
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offset=vdd_pin.ll(),
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offset=vdd_pin.ll(),
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width=self.width,
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width=self.width,
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height=vdd_pin.height())
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height=vdd_pin.height())
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@ -160,7 +157,7 @@ class dff_buf(design.design):
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# Continous gnd rail along with label.
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# Continous gnd rail along with label.
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gnd_pin=self.dff_inst.get_pin("gnd")
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gnd_pin=self.dff_inst.get_pin("gnd")
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self.add_layout_pin(text="gnd",
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self.add_layout_pin(text="gnd",
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layer="m1",
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layer=gnd_pin.layer,
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offset=gnd_pin.ll(),
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offset=gnd_pin.ll(),
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width=self.width,
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width=self.width,
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height=vdd_pin.height())
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height=vdd_pin.height())
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@ -185,17 +182,20 @@ class dff_buf(design.design):
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self.add_layout_pin_rect_center(text="Q",
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self.add_layout_pin_rect_center(text="Q",
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layer="m2",
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layer="m2",
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offset=q_pos)
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offset=q_pos)
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self.add_path("m1", [dout_pin.center(), mid_pos, q_pos])
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self.add_path(self.route_layer, [dout_pin.center(), mid_pos, q_pos])
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self.add_via_center(layers=self.m1_stack,
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self.add_via_stack_center(from_layer=dout_pin.layer,
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offset=q_pos)
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to_layer="m2",
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offset=q_pos)
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qb_pos = self.mid_qb_pos + vector(0, self.m2_pitch)
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qb_pos = self.mid_qb_pos + vector(0, self.m2_pitch)
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self.add_layout_pin_rect_center(text="Qb",
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self.add_layout_pin_rect_center(text="Qb",
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layer="m2",
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layer="m2",
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offset=qb_pos)
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offset=qb_pos)
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self.add_path("m1", [self.mid_qb_pos, qb_pos])
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self.add_path(self.route_layer, [self.mid_qb_pos, qb_pos])
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self.add_via_center(layers=self.m1_stack,
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a2_pin = self.inv2_inst.get_pin("A")
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offset=qb_pos)
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self.add_via_stack_center(from_layer=a2_pin.layer,
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to_layer="m2",
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offset=qb_pos)
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def get_clk_cin(self):
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def get_clk_cin(self):
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"""Return the total capacitance (in relative units) that the clock is loaded by in the dff"""
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"""Return the total capacitance (in relative units) that the clock is loaded by in the dff"""
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