diff --git a/compiler/modules/dff_buf.py b/compiler/modules/dff_buf.py
index 0366b10b..81629771 100644
--- a/compiler/modules/dff_buf.py
+++ b/compiler/modules/dff_buf.py
@@ -7,7 +7,7 @@
 #
 import debug
 import design
-from tech import parameter
+from tech import parameter, layer
 from tech import cell_properties as props
 from vector import vector
 from globals import OPTS
@@ -52,7 +52,6 @@ class dff_buf(design.design):
     def create_layout(self):
         self.place_instances()
         self.width = self.inv2_inst.rx()
-
         self.height = self.dff.height
         self.route_wires()
         self.add_layout_pins()
@@ -120,39 +119,37 @@ class dff_buf(design.design):
         except AttributeError:
             pass
         self.inv1_inst.place(vector(self.dff_inst.rx() + well_spacing + self.well_extend_active, 0))
-        
+       
         # Add INV2 to the right
         self.inv2_inst.place(vector(self.inv1_inst.rx(), 0))
         
     def route_wires(self):
+        if "li" in layer:
+            self.route_layer = "li"
+        else:
+            self.route_layer = "m1"
+        
         # Route dff q to inv1 a
         q_pin = self.dff_inst.get_pin("Q")
         a1_pin = self.inv1_inst.get_pin("A")
-        mid_x_offset = 0.5 * (a1_pin.cx() + q_pin.cx())
-        mid1 = vector(mid_x_offset, q_pin.cy())
-        mid2 = vector(mid_x_offset, a1_pin.cy())
-        self.add_path("m3", [q_pin.center(), mid1, mid2, a1_pin.center()])
-        self.add_via_center(layers=self.m2_stack,
-                            offset=q_pin.center())
-        self.add_via_center(layers=self.m2_stack,
-                            offset=a1_pin.center())
-        self.add_via_center(layers=self.m1_stack,
-                            offset=a1_pin.center())
+        mid1 = vector(a1_pin.cx(), q_pin.cy())
+        self.add_path(q_pin.layer, [q_pin.center(), mid1, a1_pin.center()])
+        self.add_via_stack_center(from_layer=a1_pin.layer,
+                                  to_layer=q_pin.layer,
+                                  offset=a1_pin.center())
 
         # Route inv1 z to inv2 a
         z1_pin = self.inv1_inst.get_pin("Z")
         a2_pin = self.inv2_inst.get_pin("A")
-        mid_x_offset = 0.5 * (z1_pin.cx() + a2_pin.cx())
-        self.mid_qb_pos = vector(mid_x_offset, z1_pin.cy())
-        mid2 = vector(mid_x_offset, a2_pin.cy())
-        self.add_path("m1", [z1_pin.center(), self.mid_qb_pos, mid2, a2_pin.center()])
+        self.mid_qb_pos = vector(0.5 * (z1_pin.cx() + a2_pin.cx()), z1_pin.cy())
+        self.add_zjog(z1_pin.layer, z1_pin.center(), a2_pin.center())
         
     def add_layout_pins(self):
 
         # Continous vdd rail along with label.
         vdd_pin=self.dff_inst.get_pin("vdd")
         self.add_layout_pin(text="vdd",
-                            layer="m1",
+                            layer=vdd_pin.layer,
                             offset=vdd_pin.ll(),
                             width=self.width,
                             height=vdd_pin.height())
@@ -160,7 +157,7 @@ class dff_buf(design.design):
         # Continous gnd rail along with label.
         gnd_pin=self.dff_inst.get_pin("gnd")
         self.add_layout_pin(text="gnd",
-                            layer="m1",
+                            layer=gnd_pin.layer,
                             offset=gnd_pin.ll(),
                             width=self.width,
                             height=vdd_pin.height())
@@ -185,17 +182,20 @@ class dff_buf(design.design):
         self.add_layout_pin_rect_center(text="Q",
                                         layer="m2",
                                         offset=q_pos)
-        self.add_path("m1", [dout_pin.center(), mid_pos, q_pos])
-        self.add_via_center(layers=self.m1_stack,
-                            offset=q_pos)
+        self.add_path(self.route_layer, [dout_pin.center(), mid_pos, q_pos])
+        self.add_via_stack_center(from_layer=dout_pin.layer,
+                                  to_layer="m2",
+                                  offset=q_pos)
 
         qb_pos = self.mid_qb_pos + vector(0, self.m2_pitch)
         self.add_layout_pin_rect_center(text="Qb",
                                         layer="m2",
                                         offset=qb_pos)
-        self.add_path("m1", [self.mid_qb_pos, qb_pos])
-        self.add_via_center(layers=self.m1_stack,
-                            offset=qb_pos)
+        self.add_path(self.route_layer, [self.mid_qb_pos, qb_pos])
+        a2_pin = self.inv2_inst.get_pin("A")
+        self.add_via_stack_center(from_layer=a2_pin.layer,
+                                  to_layer="m2",
+                                  offset=qb_pos)
          
     def get_clk_cin(self):
         """Return the total capacitance (in relative units) that the clock is loaded by in the dff"""
diff --git a/technology/freepdk45/gds_lib/dff.gds b/technology/freepdk45/gds_lib/dff.gds
index 526a1861..2a6004d1 100644
Binary files a/technology/freepdk45/gds_lib/dff.gds and b/technology/freepdk45/gds_lib/dff.gds differ