mirror of https://github.com/VLSIDA/OpenRAM.git
Remove latex template from repository
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Matt Guthaus
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.DS_Store
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*.bak
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openram.pdf
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main.aux
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main.bbl
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main.blg
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#To create a PDF version of the paper, named: openram.pdf,
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#use this command: ./t.sh
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#
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#This script is used to correctly setup the references/bib
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#for the paper and uses pdflatex to create the PDF.
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#
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#DEBUGGING:
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#If the generation of the PDF failed, read the error messages
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#and line numbers and use these keyboard commands to get out
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#of the current error messages: Ctrl+D
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\begin{abstract}
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Computer systems research is often inhibited by the availability of
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memory designs. Existing Process Design Kits (PDKs) frequently lack
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memory compilers, while expensive commercial solutions only provide
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memory models with immutable cells, limited configurations, and
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restrictive licenses. Manually creating memories can be time consuming
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and tedious and the designs are usually inflexible. This paper
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introduces OpenRAM, an open-source memory compiler, that provides a
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platform for the generation, characterization, and verification of
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fabricable memory designs across various technologies, sizes, and
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configurations. It enables research in computer architecture,
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system-on-chip design, memory circuit and device research, and
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computer-\allowbreak aided design.
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\end{abstract}
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\section{Acknowledgments}
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\label{sec:acknowledgements}
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This material is based upon work supported by the National Science
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Foundation under Grant No. CNS-1205685 and CNS-1205493. Many students
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have contributed to the project throughout their studies including
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Jeff Butera, Tom Golubev, Seokjoong Kim, Matthew Gaalswyk, and Son
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Bui.
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%%
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%% This is file `acmcopyright.sty',
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%%
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%% The original source files were:
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%% acmcopyright.dtx (with options: `style')
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%%
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%% IMPORTANT NOTICE:
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%%
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%% For the copyright see the source file.
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%%
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%% Any modified versions of this file must be renamed
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%% with new filenames distinct from acmcopyright.sty.
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%%
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%% For distribution of the original source see the terms
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%% for copying and modification in the file acmcopyright.dtx.
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%%
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%% This generated file may be distributed as long as the
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%% original source files, as listed above, are part of the
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\NeedsTeXFormat{LaTeX2e}
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[2014/06/29 v1.2 Copyright statemens for ACM classes]
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\ifcase\acm@copyrightmode\relax % none
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\or % acmcopyright
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ACM.
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\or % acmlicensed
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Copyright held by the owner/author(s). Publication rights licensed to
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ACM.
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\or % rightsretained
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Copyright held by the owner/author(s).
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\or % usgov
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ACM.
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Crown in Right of Canada.
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ACM.
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Copyright held by the owner/author(s). Publication rights licensed to
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ACM.
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Copyright held by the owner/author(s). Publication rights licensed to
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ACM.
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Permission to make digital or hard copies of all or part of this
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that copies are not made or distributed for profit or commercial
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advantage and that copies bear this notice and the full citation on
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the first page. Copyrights for components of this work owned by
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others than ACM must be honored. Abstracting with credit is
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permitted. To copy otherwise, or republish, to post on servers or to
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redistribute to lists, requires prior specific permission
|
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and\hspace*{.5pt}/or a fee. Request permissions from
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permissions@acm.org.
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\or % acmlicensed
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Permission to make digital or hard copies of all or part of this
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work for personal or classroom use is granted without fee provided
|
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that copies are not made or distributed for profit or commercial
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advantage and that copies bear this notice and the full citation on
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the first page. Copyrights for components of this work owned by
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others than the author(s) must be honored. Abstracting with credit
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is permitted. To copy otherwise, or republish, to post on servers
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or to redistribute to lists, requires prior specific permission
|
||||
and\hspace*{.5pt}/or a fee. Request permissions from
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permissions@acm.org.
|
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\or % rightsretained
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Permission to make digital or hard copies of part or all of this work
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||||
for personal or classroom use is granted without fee provided that
|
||||
copies are not made or distributed for profit or commercial advantage
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and that copies bear this notice and the full citation on the first
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page. Copyrights for third-party components of this work must be
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honored. For all other uses, contact the
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owner\hspace*{.5pt}/author(s).
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\or % usgov
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This paper is authored by an employee(s) of the United States
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Government and is in the public domain. Non-exclusive copying or
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redistribution is allowed, provided that the article citation is
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given and the authors and agency are clearly identified as its
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source.
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\or % usgovmixed
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ACM acknowledges that this contribution was authored or co-authored
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by an employee, or contractor of the national government. As such,
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the Government retains a nonexclusive, royalty-free right to
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publish or reproduce this article, or to allow others to do so, for
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Government purposes only. Permission to make digital or hard copies
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for personal or classroom use is granted. Copies must bear this
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notice and the full citation on the first page. Copyrights for
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components of this work owned by others than ACM must be
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honored. To copy otherwise, distribute, republish, or post,
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requires prior specific permission and\hspace*{.5pt}/or a
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fee. Request permissions from permissions@acm.org.
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\or % cagov
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This article was authored by employees of the Government of Canada.
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As such, the Canadian government retains all interest in the
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copyright to this work and grants to ACM a nonexclusive,
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royalty-free right to publish or reproduce this article, or to allow
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others to do so, provided that clear attribution is given both to
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the authors and the Canadian government agency employing them.
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Permission to make digital or hard copies for personal or classroom
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use is granted. Copies must bear this notice and the full citation
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on the first page. Copyrights for components of this work owned by
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others than the Canadain Government must be honored. To copy
|
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otherwise, distribute, republish, or post, requires prior specific
|
||||
permission and\hspace*{.5pt}/or a fee. Request permissions from
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permissions@acm.org.
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\or % cagovmixed
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ACM acknowledges that this contribution was co-authored by an
|
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affiliate of the national government of Canada. As such, the Crown
|
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in Right of Canada retains an equal interest in the copyright.
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Reprints must include clear attribution to ACM and the author's
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government agency affiliation. Permission to make digital or hard
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copies for personal or classroom use is granted. Copies must bear
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this notice and the full citation on the first page. Copyrights for
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components of this work owned by others than ACM must be honored.
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To copy otherwise, distribute, republish, or post, requires prior
|
||||
specific permission and\hspace*{.5pt}/or a fee. Request permissions
|
||||
from permissions@acm.org.
|
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\or % licensedusgovmixed
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Publication rights licensed to ACM. ACM acknowledges that this
|
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contribution was authored or co-authored by an employee, contractor
|
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or affiliate of the United States government. As such, the
|
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Government retains a nonexclusive, royalty-free right to publish or
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reproduce this article, or to allow others to do so, for Government
|
||||
purposes only.
|
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\or % licensedcagovmixed
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Publication rights licensed to ACM. ACM acknowledges that this
|
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contribution was authored or co-authored by an employee, contractor
|
||||
or affiliate of the national government of Canada. As such, the
|
||||
Government retains a nonexclusive, royalty-free right to publish or
|
||||
reproduce this article, or to allow others to do so, for Government
|
||||
purposes only.
|
||||
\or % othergov
|
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ACM acknowledges that this contribution was authored or co-authored
|
||||
by an employee, contractor or affiliate of a national government. As
|
||||
such, the Government retains a nonexclusive, royalty-free right to
|
||||
publish or reproduce this article, or to allow others to do so, for
|
||||
Government purposes only.
|
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\or % licensedothergov
|
||||
Publication rights licensed to ACM. ACM acknowledges that this
|
||||
contribution was authored or co-authored by an employee, contractor
|
||||
or affiliate of a national government. As such, the Government
|
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retains a nonexclusive, royalty-free right to publish or reproduce
|
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this article, or to allow others to do so, for Government purposes
|
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only.
|
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%%
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%% End of file `acmcopyright.sty'.
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\appendix
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\section{Architecture}
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\label{sec:architecture}
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% Overview of SRAM blocks
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The OpenRAM SRAM architecture is based on a bank of memory cells
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with peripheral circuits and control logic as illustrated in
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Figure~\ref{fig:structure}. These are further refined into eight major
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blocks: the bit-cell array, the address decoder, the word-line drivers,
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the column multiplexer, the pre-charge circuitry, the sense amplifier,
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the write drivers, and the control logic.
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\begin{figure}[tb]
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\centering
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\includegraphics[width=8cm]{./figs/sram_structure.pdf}
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\caption{An OpenRAM SRAM consists of a bit-cell array along with decoder,
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reading and writing circuitry and control logic timed with a replica
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bit-line.
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\label{fig:structure}}
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\end{figure}
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% we don't implement these yet, so don't give a tutorial on them
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%% General memories and Register Files (RF) are both examples of what an
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%% memory compiler can generate. General memories usually have shared
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%% read/write ports whereas RFs typically have separate ports. All of
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%% these options are permitted through the use of different types of
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%% memory cells such as 6, 8, and 12 transistor (T) cells which contains
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%% 1-4 access transistor pairs and their associated bit-lines. Some basic
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%% memory array options are available below:
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%% \begin{itemize}
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%% \setlength{\itemsep}{0pt} \setlength{\parskip}{0pt}
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%% \item Standard 6T cell for single-port memory
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%% \item Dual-port 8T cell for dual-port memory or separate read/write ports
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%% \item Four-port 12T cell for dual separate read/write ports
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%% \item Custom sense amplifier designs for different performances
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%% \item Different types of address decoders for different performances
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%% \end{itemize}
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\begin{figure*}[tb]
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\centering
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\subfigure[Read operation timing]{
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\includegraphics[width = 8cm]{figs/timing_read.pdf}
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\label{fig:timing_read}}
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\subfigure[Write operation timing]{
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\includegraphics[width = 8cm]{figs/timing_write.pdf}
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\label{fig:timing_write}}
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\caption{OpenRAM uses a synchronous SRAM interface using a system
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clock (clk) along with control signals: output enable (OEb), chip
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select (CSb) and write enable (WEb).}
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\label{fig:timing}
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\end{figure*}
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{\bf Bit-cell Array:} In the initial release of OpenRAM, the $6$T cell
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is the default memory cell because it is the most commonly used cell
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in SRAM devices. $6$T cells are tiled together with abutting word- and
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bit-lines to make up the memory array. The bit-cell array's aspect
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ratio is made as square as possible using multiple columns of data
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words. The memory cell is a custom designed library cell for each technology.
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Other types of memory cells, such as $7$T, $8$T, and $10$T cells, can be used
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as alternatives to the $6$T cell.
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{\bf Address Decoder:} The address decoder takes the row address bits
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as inputs and asserts the appropriate word-line so that the correct
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memory cells can be read from or written to. The address decoder is
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placed to the left of the memory array and spans the array's vertical
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length. Different types of decoders can be used such as an included
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dynamic NAND decoder, but OpenRAM's default option is a hierarchical CMOS
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decoder.
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{\bf Word-Line Driver:} Word-line drivers are inserted between the
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address decoder and the memory array as buffers. The word-line drivers
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are sized based on the width of the memory array so that they can drive
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the row select signal across the bit-cell array.
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{\bf Column Multiplexer:} The column multiplexer is an optional block
|
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that uses the lower address bits to select the associated word in a
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row. The column mux is dynamically generated and can be omitted or can
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have 2 or 4 inputs. Larger column muxes are possible, but are not
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frequently used in memories. There are options for a multi-level tree
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mux as well.
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{\bf Bit-line Precharge:} This circuitry pre-charges
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the bit-lines during the first phase of the clock for read
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operations. The precharge circuit is placed on top of every column in
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the memory array and equalizes the bit-line voltages so that the
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sense amplifier can sense the voltage difference between the two
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bit-lines.
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{\bf Sense Amplifier:} A differential sense amplifier is used to sense
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the voltage difference between the bit-lines of a memory cell while a
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read operation is performed. The sense amplifier uses a bit-line
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isolation technique to increase performance. The sense amplifier
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circuitry is placed below the column multiplexer or the memory
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array if no column multiplexer is used. There is one sense amplifier for
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each output bit.
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{\bf Write Driver:} The write drivers send the input data signals onto the
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bit-lines for a write operation. The write drivers are tri-stated
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so that they can be placed between the column multiplexer/memory array
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and the sense amplifiers. There is one write driver for each input
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data bit.
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%% \subsubsection{Bit-cell and Bit-cell Array}
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%% A bit-cell class is provided to instantiate the custom designed memory
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%% cell located in the technology directory. Then the bit-cell array class
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%% will take the single bit-cell instance to dynamically generate the
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%% memory array. Using the functionality of GdsMill, we can rotate and/or
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%% mirror an instance. Doing so, will allow us to abut the power rails.
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%% \subsubsection{Address Decoder}
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%% The hierarchical decoder is the default row address decoder that is
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%% used in OpenRAM. The hierarchical decoder is dynamically generated
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%% using the inverter and NAND gates with the help of basic shapes. The
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%% height of each decoder row will match the height of the memory cell so
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%% that the power rails can be abutted. OpenRAM also provides a NAND
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%% decoder as an alternative. NAND decoder uses NMOS and PMOS transistors
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%% created by ptx class. User can define type of the decoder in the
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%% configuration file.
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%% \subsubsection{Word-line Driver}
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%% The word-line driver will be a column of alternating "mirrored"
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%% inverters instances that is used to drive the signal to access the
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%% memory cells in the row. The inverters will be sized accordingly
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%% depending on the size of the memory array.
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%% \subsubsection{Column Multiplexer}
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%% The column multiplexer is an optional block that is used depending on
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%% the size of the memory array. By generating an instance of a 1-1
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%% multiplexer, we can then tile them to create bigger multiplexers such
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%% as 2-1, 4-1, etc. OpenRAM has two options for column multiplexing.
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%% Single-level-column-mux is the default column multiplexer but user can
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%% choose Tree-Column-Mux in configuration file. Both multiplexers use
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%% transistors created by ptx class.
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%% \subsubsection{Precharge and Precharge Array}
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%% The precharge circuitry is dynamically generated using the transistor
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%% instances and various basic shapes. The precharge class dynamically
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%% generates an instance for a single column. The precharge array class
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%% takes that instance and tiles them horizontally to match the number of
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%% columns in the memory array. The width of the precharge cell is
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%% determined by the width of the user-created memory cell.
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%% \subsubsection{Sense Amplifier and Sense Amplifier Array}
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%% The sense amplifier is user-designed analog circuit that is placed in
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%% the technology directory. The sense amplifier class instantiates the
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%% library cell and the sense amplifier array takes that instance to
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%% create a horizontal array matching the number of output bits for the
|
||||
%% memory. When designing this library cell, the user should match this
|
||||
%% cell's width and bit-lines to the memory cell's.
|
||||
|
||||
%% \subsubsection{Write Driver and Write Driver Array}
|
||||
%% Similar to the precharge classes, the write driver class will generate
|
||||
%% an instance for a single bit and the write driver array will tile them
|
||||
%% horizontally to match the number of input bits for the memory. The
|
||||
%% write drivers will be dynamically sized accordingly based on the size
|
||||
%% of the memory array.
|
||||
|
||||
%% \subsubsection{Control Logic}
|
||||
%% There will be a control logic module that will arrange the
|
||||
%% master-slave flip-flops and the logic associated with the control
|
||||
%% signals into a single design. Flip-flops are used to drive the control
|
||||
%% signals and standard library cells such as NAND and NOR gates will be
|
||||
%% used for the logic. A RBL is also generated using parameterized gates
|
||||
%% and Replica Cell (RC). RC is a 6T SRAM memory cell which is hard-wired
|
||||
%% to store a zero in order to discharge the RBL and generate the sense
|
||||
%% amplifier enable signal in read mode.
|
||||
|
||||
%% \subsubsection{Additional Arrays}
|
||||
%% In addition to the eight main blocks, there are helper modules that
|
||||
%% help simplify the designs in the eight main blocks. We have a
|
||||
%% flip-flop array class that takes the custom designed master-slave
|
||||
%% flip-flop library cell to create a tiled array. We also have the
|
||||
%% tri-state array class that will generate the array of tri-states for
|
||||
%% the DATA bus.
|
||||
|
||||
% Overview of signal inputs and timing
|
||||
{\bf Control Logic:} The OpenRAM SRAM architecture incorporates a
|
||||
standard synchronous memory interface using a system clock (clk). The
|
||||
control logic uses an externally provided, active-low output enable
|
||||
(OEb), chip select (CSb), and write enable (WEb) to combine multiple
|
||||
SRAMs into a larger structure. Internally, the OpenRAM compiler can
|
||||
have $1$, $2$, or $4$ memory banks to amortize the area/power cost of
|
||||
control logic and peripheral circuitry.
|
||||
|
||||
All of the input control signals are stored using master-slave (MS)
|
||||
flip-flops (FF) to ensure that the signals are valid for the entire
|
||||
clock cycle. During a read operation, data is available after the
|
||||
negative clock edge (second half of cycle) as shown in
|
||||
Figure~\ref{fig:timing_read}. To avoid dead cycles which degrade
|
||||
performance, a Zero Bus Turn-around (ZBT) technique is used in OpenRAM
|
||||
timing. The ZBT enables higher memory throughput since there are no
|
||||
wait states. During ZBT writes, data is set up before the negative
|
||||
clock edge and is captured on the negative edge. Figure~\ref{fig:timing_write}
|
||||
shows the timing for input signals during the write operation.
|
||||
|
||||
The internal control signals are generated using a replica bit-line (RBL)
|
||||
structure for the timing of the sense amplifier enable and output
|
||||
data storage~\cite{RBL:1998}. The RBL turns on the sense amplifiers
|
||||
at the exact time in presence of process variability in sub-$100$nm
|
||||
technologies.
|
||||
|
||||
|
|
@ -1,93 +0,0 @@
|
|||
\section{Background}
|
||||
\label{sec:background}
|
||||
% brief origin/background of memory compilers
|
||||
|
||||
% Existence of memory compilers from the beginning
|
||||
Memory compilers have been used in Electronic Design Automation (EDA)
|
||||
design flows to reduce the design
|
||||
time long before contemporary
|
||||
compilers~\cite{broderson:sicompiler,johannsen:blocks}.
|
||||
However, these compilers were generally not portable as they were
|
||||
nothing more
|
||||
than quick scripts to aid designers. Porting to a new technology
|
||||
essentially required rewriting the scripts. However, the increase in
|
||||
design productivity when porting designs between technologies has led to
|
||||
more research on memory array
|
||||
compilers~\cite{cabe:flexible,huang:array,poechmueller:array,Xu:2007}.
|
||||
|
||||
% Reason why compilers evolved to today's current version
|
||||
As technology entered the Deep Sub-Micron (DSM) era, memory designs
|
||||
became one of the most challenging parts of circuit design
|
||||
due to decreasing static noise margins (SNM), increasing fabrication
|
||||
variability, and increasing leakage power consumption.
|
||||
This increased the complexity of memory compilers dramatically as they had to
|
||||
adapt to the ever-changing technologies. Simultaneously, design
|
||||
methodologies shifted from silicon compilers to standard cell place
|
||||
and route methods which required large optimized libraries. During
|
||||
this time, industry began using third-party suppliers of standard cell
|
||||
libraries and memory compilers that allowed their reuse to amortize
|
||||
development costs. These next-generation memory compilers provided
|
||||
silicon-verification that allowed designers to focus on their new
|
||||
design contribution rather than time-consuming tasks such as memory
|
||||
generation.
|
||||
|
||||
% Commercial industry memory compilers' description and cost
|
||||
Contemporary memory compilers have been widely used by industry, but
|
||||
the internal operation is typically hidden. Several prominent
|
||||
companies and foundries have provided memory compilers to their
|
||||
customers. These memory compilers usually allow customers to view
|
||||
front-end simulation, timing/power values, and pin locations after a
|
||||
license agreement is signed. Back-end features such as layout are
|
||||
normally supplied directly to the fab and are only given to the user
|
||||
for a licensing fee.
|
||||
|
||||
% Examples of commercial compilers' drawbacks
|
||||
Specifically, Global Foundries offers front-end PDKs for free, but not
|
||||
back-end detailed views~\cite{globalfoundries:2015}. Faraday
|
||||
Technologies provides a \enquote{black box} design kit where users do
|
||||
not know the details of the internal memory
|
||||
design~\cite{faraday:2015}. Dolphin Technology offers closed-source
|
||||
compilers which can create RAMs, ROMs, and CAMs for a variety of
|
||||
technologies~\cite{dolphin:2015}. The majority of these commercial
|
||||
compilers do not allow the customer to alter the base design, are
|
||||
restricted by the company's license, and usually require a fee. This
|
||||
makes them virtually unavailable and not useful for many academic
|
||||
research projects.
|
||||
|
||||
% Describe the problem (no free open-source that is widely distributed)
|
||||
In addition to memory compilers provided by industry, various research
|
||||
groups have released scripts to generate memories. However, these
|
||||
designs are not silicon verified and are usually only composed of
|
||||
simple structures. For example, FabMem is able to
|
||||
create small arrays, but it is highly dependent on the Cadence design
|
||||
tools~\cite{fabmem:2010}. The scripts do not provide any characterization capability
|
||||
and cannot easily integrate with commercial place and route tools.
|
||||
|
||||
% Industry's attempt to provide academia a memory compiler
|
||||
Another recent, promising solution for academia is the Synopsys
|
||||
Generic Memory Compiler (GMC)~\cite{Goldman:2014}. The software is
|
||||
provided with sample generic libraries such as Synopsys' $32$/$28$nm and
|
||||
$90$nm abstract technologies and can generate the entire SRAM for these
|
||||
technologies. The GMC generates GDSII layout data, SPICE netlists,
|
||||
Verilog and VHDL models, timing/power libraries, and DRC/LVS
|
||||
verification reports. GMC, however, is not recommended for
|
||||
fabrication since the technologies it supports are not real. Its sole
|
||||
purpose is to aid students in VLSI courses to learn about using
|
||||
memories in design flows.
|
||||
|
||||
% Academia's' attempts at a memory compiler
|
||||
There have been multiple attempts by academia to implement a memory
|
||||
compiler that is not restricted: the Institute of
|
||||
Microelectronics' SRAM IP Compiler~\cite{Xu:2007}, School of
|
||||
Electronic Science and Engineering at Southeast University's Memory IP
|
||||
Compiler~\cite{Chen:2012}, and Tsinghua University's Low Power SRAM
|
||||
Compiler~\cite{Wu:2010}. These are all methodologies and design flows
|
||||
for a memory compiler, but there are no public releases.
|
||||
|
||||
% State what we are looking for in academia. -- duplicate from introduction
|
||||
%% With all these attempts, there still isn't a complete solution for
|
||||
%% academia's research needs. Researchers need a memory compiler that is
|
||||
%% open-source, platform- and tool-portable, technology independent, and
|
||||
%% can generate fabricable memory designs.
|
||||
|
||||
|
||||
Binary file not shown.
|
|
@ -1,21 +0,0 @@
|
|||
\section{Conclusions}
|
||||
\label{sec:conclusions}
|
||||
This paper introduced OpenRAM, an open-source and portable memory
|
||||
compiler. OpenRAM generates the circuit, functional model, and layout
|
||||
of variable-sized SRAMs. In addition, a memory characterizer
|
||||
provides synthesis timing/power models.
|
||||
|
||||
The main motivation behind OpenRAM is to promote and simplify
|
||||
memory-related research in academia. Since OpenRAM is open-sourced,
|
||||
flexible, and portable, this memory compiler can be adapted to various
|
||||
technologies and is easily modified to address specific design
|
||||
requirements. Therefore, OpenRAM provides a platform to implement and test
|
||||
new memory designs.
|
||||
|
||||
Designs are currently being fabricated to test designs using the
|
||||
OpenRAM framework in SCMOS. We are also continuously introducing new
|
||||
features, such as non-6T memories, variability characterization,
|
||||
word-line segmenting, characterization speed-up, and a graphical user
|
||||
interface (GUI). We hope to engage an active community in the future
|
||||
development of OpenRAM.
|
||||
|
||||
|
|
@ -1,5 +0,0 @@
|
|||
#!/bin/bash
|
||||
psfile=${1%.pdf}.ps
|
||||
gs -dSAFER -dNOPLATFONTS -dNOPAUSE -dBATCH -sDEVICE=pdfwrite -sPAPERSIZE=letter -dCompatibilityLevel=1.4 -dPDFSETTINGS=/printer -dCompatibilityLevel=1.4 -dMaxSubsetPct=100 -dSubsetFonts=true -dEmbedAllFonts=true -sOutputFile=temp.pdf -f $1
|
||||
mv temp.pdf $1
|
||||
pdf2ps $1 $psfile
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
File diff suppressed because it is too large
Load Diff
Binary file not shown.
|
|
@ -1,55 +0,0 @@
|
|||
clc;
|
||||
|
||||
X = [ 2 , 8 , 32, 128];
|
||||
Y1_Freepdk =[0.0048413475625; 0.0135007585125;0.051075243575; 0.283865472];
|
||||
Y2_Freepdk=[0.0048094391125; 0.0135007585125; 0.0435568917; 0.2118510735];
|
||||
Y3_Freepdk=[0.0047775306625; 0.0129289229375; 0.0419903161125; 0.156997489175];
|
||||
Y4_Freepdk=[0.0052897701375; 0.0128789376875; 0.0419019176625; 0.1512635205];
|
||||
|
||||
|
||||
Y1_SCN3ME =[0.75276018; 2.08835631; 7.89312366; 40.6931238];
|
||||
Y2_SCN3ME =[0.74817639; 2.0216187; 6.804401625; 31.6371744];
|
||||
Y3_SCN3ME =[0.7435926; 2.01449475; 6.62959215; 24.64420014];
|
||||
Y4_SCN3ME =[0.83660283; 2.0073708; 6.61707036; 23.839544025];
|
||||
|
||||
Y1_T_Freepdk =[0.861; 1.32; 1.8; 2.2];
|
||||
Y2_T_Freepdk =[1.02; 1.33; 1.83; 2.6];
|
||||
Y3_T_Freepdk =[0.86; 1.5; 1.9; 6.75];
|
||||
Y4_T_Freepdk =[1.076; 1.34; 2.01; 9.86];
|
||||
|
||||
Y1_T_SCN3ME =[9.42; 8.25; 11.69; 12.7];
|
||||
Y2_T_SCN3ME =[11.82; 16.04; 14.7; 18.21];
|
||||
Y3_T_SCN3ME =[14.81; 19.24; 23.82; 30.25];
|
||||
Y4_T_SCN3ME =[22.9; 23.12; 30.75; 44.95];
|
||||
|
||||
|
||||
subplot(4,1,1)
|
||||
plot (X, Y1_Freepdk, X, Y2_Freepdk, X, Y3_Freepdk, X, Y4_Freepdk,'LineWidth',2);
|
||||
grid on;
|
||||
ylabel('Area (mm^2)','FontSize',12, 'Color','k');
|
||||
xlabel('Total Size (Kbits)','FontSize',12, 'Color','k');
|
||||
subplot(4,1,2)
|
||||
plot (X, Y1_SCN3ME, X, Y2_SCN3ME, X, Y3_SCN3ME, X, Y4_SCN3ME,'LineWidth',2);
|
||||
grid on;
|
||||
ylabel('Area (mm^2)','FontSize',12, 'Color','k');
|
||||
xlabel('Total Size (Kbits)','FontSize',12, 'Color','k');
|
||||
subplot(4,1,3)
|
||||
plot (X, Y1_T_Freepdk, X, Y2_T_Freepdk, X, Y3_T_Freepdk, X, Y4_T_Freepdk,'LineWidth',2);
|
||||
grid on;
|
||||
ylabel('Access time (ns)','FontSize',12, 'Color','k');
|
||||
xlabel('Total Size (Kbits)','FontSize',12, 'Color','k');
|
||||
subplot(4,1,4)
|
||||
plot (X, Y1_T_SCN3ME, X, Y2_T_SCN3ME, X, Y3_T_SCN3ME, X, Y4_T_SCN3ME,'LineWidth',2);
|
||||
ylabel('Access time (ns)','FontSize',12, 'Color','k');
|
||||
xlabel('Total Size (Kbits)','FontSize',12, 'Color','k');
|
||||
|
||||
|
||||
grid on;
|
||||
legend({'16-bit word size', '32-bit word size','64-bit word size', '128-bit word size'},'Location','northwest','orientation', 'vertical' , 'FontSize',12, 'LineWidth',1.2);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
|
|
@ -1,14 +0,0 @@
|
|||
set terminal pdf dashed
|
||||
set output "../Freepdk_Area.pdf"
|
||||
set palette color
|
||||
set xlabel "Total Size (Kbit)"
|
||||
set ylabel "Area (mm^2)"
|
||||
set key below
|
||||
plot 'freepdk45_size.dat' using ($1/1024):($2/1e6) with line title '16-bit word' lt 0 lw 5 lc 0 ,\
|
||||
'freepdk45_size.dat' using ($1/1024):($2/1e6) with points title '' lt 0 lw 5 lc 0 ,\
|
||||
'freepdk45_size.dat' using ($1/1024):($3/1e6) with line title '32-bit word' lt 1 lw 5 lc 1 ,\
|
||||
'freepdk45_size.dat' using ($1/1024):($3/1e6) with points title '' lt 1 lw 5 lc 1 ,\
|
||||
'freepdk45_size.dat' using ($1/1024):($4/1e6) with line title '64-bit word' lt 2 lw 5 lc 2 ,\
|
||||
'freepdk45_size.dat' using ($1/1024):($4/1e6) with points title '' lt 2 lw 5 lc 2 ,\
|
||||
'freepdk45_size.dat' using ($1/1024):($5/1e6) with line title '128-bit word' lt 3 lw 5 lc 3 ,\
|
||||
'freepdk45_size.dat' using ($1/1024):($5/1e6) with points title '' lt 3 lw 5 lc 3
|
||||
|
|
@ -1,7 +0,0 @@
|
|||
|
||||
2048 4841.3475625 4809.4391125 4777.5306625 5289.7701375
|
||||
8192 13500.7585125 12978.9081875 12928.9229375 12878.9376875
|
||||
#16384 25605.7869 22997.2777125 22908.8792625 22820.4808125
|
||||
32768 51075.243575 43556.8917 41990.3161125 41901.9176625
|
||||
#65536 142381.5903 86382.658775 79459.1013 79292.00325
|
||||
131072 283865.472 211851.0735 156997.489175 151263.5205
|
||||
|
|
@ -1,14 +0,0 @@
|
|||
set terminal pdf dashed
|
||||
set output "../Scn3me_Area.pdf"
|
||||
set palette color
|
||||
set xlabel "Total Size (Kbit)"
|
||||
set ylabel "Area (mm^2)"
|
||||
set key below
|
||||
plot 'scn3me_size.dat' using ($1/1024):($2/1e6) with line title '16-bit word' lt 0 lw 5 lc 0 ,\
|
||||
'scn3me_size.dat' using ($1/1024):($2/1e6) with points title '' lt 0 lw 5 lc 0 ,\
|
||||
'scn3me_size.dat' using ($1/1024):($3/1e6) with line title '32-bit word' lt 1 lw 5 lc 1 ,\
|
||||
'scn3me_size.dat' using ($1/1024):($3/1e6) with points title '' lt 1 lw 5 lc 1 ,\
|
||||
'scn3me_size.dat' using ($1/1024):($4/1e6) with line title '64-bit word' lt 2 lw 5 lc 2 ,\
|
||||
'scn3me_size.dat' using ($1/1024):($4/1e6) with points title '' lt 2 lw 5 lc 2 ,\
|
||||
'scn3me_size.dat' using ($1/1024):($5/1e6) with line title '128-bit word' lt 3 lw 5 lc 3 ,\
|
||||
'scn3me_size.dat' using ($1/1024):($5/1e6) with points title '' lt 3 lw 5 lc 3
|
||||
|
|
@ -1,5 +0,0 @@
|
|||
|
||||
2048 752760.18 748176.39 743592.6 836602.83
|
||||
8192 2088356.31 2021618.7 2014494.75 2007370.8
|
||||
32768 7893123.66 6804401.625 6629592.15 6617070.36
|
||||
131072 40693123.8 31637174.4 24644200.14 23839544.025
|
||||
|
|
@ -1,100 +0,0 @@
|
|||
#!/usr/bin/gnuplot
|
||||
#
|
||||
# Demonstration of a common use scenario of the multiplot environment.
|
||||
#
|
||||
# AUTHOR: Hagen Wierstorf
|
||||
#
|
||||
|
||||
reset
|
||||
|
||||
set terminal pdf dashed size 8cm,12cm
|
||||
set output "Results.pdf"
|
||||
set palette color
|
||||
|
||||
unset key
|
||||
|
||||
# Enable the use of macros
|
||||
set macros
|
||||
|
||||
# MACROS
|
||||
# Margins for each row resp. column
|
||||
# top of top fig, bottom of top fig
|
||||
TMARGIN = "set tmargin at screen 0.9; set bmargin at screen 0.575"
|
||||
# top of lower fig, bottom of lower fig
|
||||
BMARGIN = "set tmargin at screen 0.525; set bmargin at screen 0.15"
|
||||
# left of left fig, right of left fig
|
||||
LMARGIN = "set lmargin at screen 0.1; set rmargin at screen 0.48"
|
||||
# left point of right fig ,right most
|
||||
RMARGIN = "set lmargin at screen 0.52; set rmargin at screen 0.9"
|
||||
|
||||
# Placement of the a,b,c,d labels in the graphs
|
||||
POSA = "at graph 0.6,0.2 font ',5'"
|
||||
POSB = "at graph 0.5,0.2 font ',5'"
|
||||
|
||||
### Start multiplot (2x2 layout)
|
||||
set multiplot layout 4,1
|
||||
# --- GRAPH a
|
||||
set key outside center vertical top box 3
|
||||
set lmargin at screen 0.2; set rmargin at screen 0.9
|
||||
set tmargin at screen 0.88; set bmargin at screen 0.68
|
||||
#@TMARGIN; @LMARGIN
|
||||
#@NOXTICS; @YTICS
|
||||
set label 1 '45nm Area' @POSA
|
||||
set ylabel "mm^2"
|
||||
plot 'density_data/freepdk45_size.dat' using ($1/1024):($2/1e6) with line axis x1y1 title '16-bit word size' lt 0 lw 5 lc 0 ,\
|
||||
'density_data/freepdk45_size.dat' using ($1/1024):($2/1e6) with points axis x1y1 title '' lt 0 lw 5 lc 0 ,\
|
||||
'density_data/freepdk45_size.dat' using ($1/1024):($3/1e6) with line axis x1y1 title '32-bit word size' lt 1 lw 5 lc 1 ,\
|
||||
'density_data/freepdk45_size.dat' using ($1/1024):($3/1e6) with points axis x1y1 title '' lt 1 lw 5 lc 1 ,\
|
||||
'density_data/freepdk45_size.dat' using ($1/1024):($4/1e6) with line axis x1y1 title '64-bit word size' lt 2 lw 5 lc 2 ,\
|
||||
'density_data/freepdk45_size.dat' using ($1/1024):($4/1e6) with points axis x1y1 title '' lt 2 lw 5 lc 2 ,\
|
||||
'density_data/freepdk45_size.dat' using ($1/1024):($5/1e6) with line axis x1y1 title '128-bit word size' lt 3 lw 5 lc 3 ,\
|
||||
'density_data/freepdk45_size.dat' using ($1/1024):($5/1e6) with points axis x1y1 title '' lt 3 lw 5 lc 3
|
||||
|
||||
# --- GRAPH b
|
||||
unset key
|
||||
set tmargin at screen 0.68; set bmargin at screen 0.48
|
||||
#@TMARGIN; @RMARGIN
|
||||
#@NOXTICS; @NOYTICS
|
||||
set label 1 '180nm Area' @POSA
|
||||
set ylabel "mm^2"
|
||||
plot 'density_data/scn3me_size.dat' using ($1/1024):($2/1e6) with line axis x1y1 title '16-bit word size' lt 0 lw 5 lc 0 ,\
|
||||
'density_data/scn3me_size.dat' using ($1/1024):($2/1e6) with points axis x1y1 title '' lt 0 lw 5 lc 0 ,\
|
||||
'density_data/scn3me_size.dat' using ($1/1024):($3/1e6) with line axis x1y1 title '32-bit word size' lt 1 lw 5 lc 1 ,\
|
||||
'density_data/scn3me_size.dat' using ($1/1024):($3/1e6) with points axis x1y1 title '' lt 1 lw 5 lc 1 ,\
|
||||
'density_data/scn3me_size.dat' using ($1/1024):($4/1e6) with line axis x1y1 title '64-bit word size' lt 2 lw 5 lc 2 ,\
|
||||
'density_data/scn3me_size.dat' using ($1/1024):($4/1e6) with points axis x1y1 title '' lt 2 lw 5 lc 2 ,\
|
||||
'density_data/scn3me_size.dat' using ($1/1024):($5/1e6) with line axis x1y1 title '128-bit word size' lt 3 lw 5 lc 3 ,\
|
||||
'density_data/scn3me_size.dat' using ($1/1024):($5/1e6) with points axis x1y1 title '' lt 3 lw 5 lc 3
|
||||
|
||||
# --- GRAPH c
|
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set tmargin at screen 0.48; set bmargin at screen 0.28
|
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#@BMARGIN; @LMARGIN
|
||||
#@XTICS; @YTICS
|
||||
set label 1 '45nm Access time' @POSB
|
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set ylabel "ns"
|
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plot 'timing_data/freepdk45_timing.dat' using ($1/1024):2 with line axis x1y2 title '16-bit word' lt 0 lw 5 lc 0 ,\
|
||||
'timing_data/freepdk45_timing.dat' using ($1/1024):2 with points axis x1y2 title '' lt 0 lw 5 lc 0 ,\
|
||||
'timing_data/freepdk45_timing.dat' using ($1/1024):3 with line axis x1y2 title '32-bit word' lt 1 lw 5 lc 1 ,\
|
||||
'timing_data/freepdk45_timing.dat' using ($1/1024):3 with points axis x1y2 title '' lt 1 lw 5 lc 1 ,\
|
||||
'timing_data/freepdk45_timing.dat' using ($1/1024):4 with line axis x1y2 title '64-bit word' lt 2 lw 5 lc 2 ,\
|
||||
'timing_data/freepdk45_timing.dat' using ($1/1024):4 with points axis x1y2 title '' lt 2 lw 5 lc 2 ,\
|
||||
'timing_data/freepdk45_timing.dat' using ($1/1024):5 with line axis x1y2 title '128-bit word' lt 3 lw 5 lc 3 ,\
|
||||
'timing_data/freepdk45_timing.dat' using ($1/1024):5 with points axis x1y2 title '' lt 3 lw 5 lc 3
|
||||
|
||||
# --- GRAPH d
|
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set tmargin at screen 0.28; set bmargin at screen 0.08
|
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#@BMARGIN; @RMARGIN
|
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#@XTICS; @NOYTICS
|
||||
set ylabel "ns"
|
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set xlabel "Total Size (Kbits)"
|
||||
set label 1 '180nm Access time' @POSB
|
||||
plot 'timing_data/scn3me_timing.dat' using ($1/1024):2 with line axis x1y2 title '16-bit word' lt 0 lw 5 lc 0 ,\
|
||||
'timing_data/scn3me_timing.dat' using ($1/1024):2 with points axis x1y2 title '' lt 0 lw 5 lc 0 ,\
|
||||
'timing_data/scn3me_timing.dat' using ($1/1024):3 with line axis x1y2 title '32-bit word' lt 1 lw 5 lc 1 ,\
|
||||
'timing_data/scn3me_timing.dat' using ($1/1024):3 with points axis x1y2 title '' lt 1 lw 5 lc 1 ,\
|
||||
'timing_data/scn3me_timing.dat' using ($1/1024):4 with line axis x1y2 title '64-bit word' lt 2 lw 5 lc 2 ,\
|
||||
'timing_data/scn3me_timing.dat' using ($1/1024):4 with points axis x1y2 title '' lt 2 lw 5 lc 2 ,\
|
||||
'timing_data/scn3me_timing.dat' using ($1/1024):5 with line axis x1y2 title '128-bit word' lt 3 lw 5 lc 3 ,\
|
||||
'timing_data/scn3me_timing.dat' using ($1/1024):5 with points axis x1y2 title '' lt 3 lw 5 lc 3
|
||||
unset multiplot
|
||||
### End multiplot
|
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Binary file not shown.
Binary file not shown.
|
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showpage
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%%Trailer
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count op_count sub {pop} repeat
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countdictstack dict_count sub {end} repeat
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cairo_eps_state restore
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%%EOF
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Binary file not shown.
File diff suppressed because it is too large
Load Diff
|
Before Width: | Height: | Size: 51 KiB |
Binary file not shown.
File diff suppressed because it is too large
Load Diff
|
Before Width: | Height: | Size: 69 KiB |
Binary file not shown.
|
|
@ -1,14 +0,0 @@
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set terminal pdf dashed
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set output "../Freepdk_Read_Access_time.pdf"
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set palette color
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set xlabel "Total Size (Kbit)"
|
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set ylabel "Read Access time (ns)"
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set key below
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plot 'freepdk45_timing.dat' using ($1/1024):2 with line title '16-bit word' lt 0 lw 5 lc 0 ,\
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'freepdk45_timing.dat' using ($1/1024):2 with points title '' lt 0 lw 5 lc 0 ,\
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'freepdk45_timing.dat' using ($1/1024):3 with points title '' lt 1 lw 5 lc 1 ,\
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'freepdk45_timing.dat' using ($1/1024):4 with points title '' lt 2 lw 5 lc 2 ,\
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'freepdk45_timing.dat' using ($1/1024):5 with line title '128-bit word' lt 3 lw 5 lc 3 ,\
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'freepdk45_timing.dat' using ($1/1024):5 with points title '' lt 3 lw 5 lc 3
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@ -1,5 +0,0 @@
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|
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@ -1,14 +0,0 @@
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set terminal pdf dashed
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set output "../Scn3me_Read_Access_time.pdf"
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set palette color
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set xlabel "Total Size (Kbit)"
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set ylabel "Read Access time (ns)"
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set key below
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plot 'scn3me_timing.dat' using ($1/1024):2 with line title '16-bit word' lt 0 lw 5 lc 0 ,\
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'scn3me_timing.dat' using ($1/1024):4 with points title '' lt 2 lw 5 lc 2 ,\
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'scn3me_timing.dat' using ($1/1024):5 with line title '128-bit word' lt 3 lw 5 lc 3 ,\
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'scn3me_timing.dat' using ($1/1024):5 with points title '' lt 3 lw 5 lc 3
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@ -1,5 +0,0 @@
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Before Width: | Height: | Size: 33 KiB |
|
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@ -1,214 +0,0 @@
|
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\section{Implementation}
|
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\label{sec:implementation}
|
||||
|
||||
% source langauge
|
||||
OpenRAM's methodology is implemented using an object-oriented approach
|
||||
in the Python programming language. Python is a simple, yet powerful
|
||||
language that is easy to learn and very human-readable. Moreover, Python
|
||||
enables portability to most operating systems. OpenRAM has no additional
|
||||
dependencies except a DRC/LVS tool, but that is disabled with a
|
||||
warning if the tools are unavailable.
|
||||
|
||||
% portability of tools and technologies
|
||||
In addition to system portability, OpenRAM is also translatable across
|
||||
numerous process technologies. This is accomplished by using
|
||||
generalized routines to generate the memory based on common features
|
||||
across all technologies. To facilitate user modification and
|
||||
technology interoperability, OpenRAM provides a reference implementation in
|
||||
$45$nm FreePDK45~\cite{4231502} and a fabricable option using the
|
||||
MOSIS Scalable CMOS (SCMOS) design rules~\cite{scmos}. FreePDK45 uses
|
||||
many design rules found in modern technologies, but is non-fabricable,
|
||||
while SCMOS enables fabrication of designs using the MOSIS foundry
|
||||
services. SCMOS is not confidential and an implementation using it is
|
||||
included, however, it does not include many advanced DSM design
|
||||
rules. OpenRAM has also been ported to other commercial technologies,
|
||||
but these are not directly included due to licensing issues.
|
||||
|
||||
% methodology overview
|
||||
OpenRAM's framework is divided into \enquote{front-end} and \enquote{back-end}
|
||||
methodologies as shown in Figure~\ref{fig:methodology}. The front-end
|
||||
has the compiler and the characterizer. The compiler generates
|
||||
SPICE models and its GDSII layouts based on user inputs. The
|
||||
characterizer calls a SPICE simulator to produce timing and power
|
||||
results. The back-end uses a spice netlist extracted from the GDSII
|
||||
layout using to generate annotated timing and power models.
|
||||
|
||||
\begin{figure}[tb]
|
||||
\centering
|
||||
\includegraphics[width=8cm]{./figs/methodology.pdf}
|
||||
\caption{Overall Compilation and Characterization Methodology}
|
||||
\label{fig:methodology}
|
||||
\end{figure}
|
||||
|
||||
%\fixme{We actually dont have back end done yet.}
|
||||
|
||||
\subsection{Base Data Structures}
|
||||
|
||||
The design modules in OpenRAM are derived from the {\it design} class
|
||||
(design.py). The design class has a name, a SPICE model (netlist), and
|
||||
a layout. Both the SPICE model and the layout inherit their
|
||||
capabilities from a hierarchical class. The design class also provides
|
||||
inherited functions to perform DRC and LVS verification of any
|
||||
sub-design for hierarchical debugging.
|
||||
|
||||
The design class derives from the {\it spice} class
|
||||
(hierarchy\_\allowbreak spice.py) which has a data structure to
|
||||
maintain the circuit hierarchy. This class maintains the design
|
||||
instances, their pins, and their connections as well as helper
|
||||
functions to maintain the structure and connectivity of the circuit
|
||||
hierarchy.
|
||||
|
||||
The design class also derives from a {\it layout} class (hierarchy\_layout.py).
|
||||
This class has a list of physical instances of sub-modules in the layout and
|
||||
a structure for simple objects such as shapes and labels in the
|
||||
current hierarchy level. In addition, there are helper functions that
|
||||
maintain the physical layout structures.
|
||||
|
||||
OpenRAM has an integrated, custom GDSII library to read, write, and
|
||||
manipulate GDSII files. The library, originally called
|
||||
GdsMill~\cite{gdsmill}, has been modified, debugged, and extended for
|
||||
OpenRAM. Full rights were given to include the GdsMill source with
|
||||
OpenRAM, but to make the interfacing easier and porting to other
|
||||
physical layout databases possible, OpenRAM implements a {\it
|
||||
geometry} wrapper class (geometry.py) that abstracts the GdsMill
|
||||
library.
|
||||
|
||||
\subsection{Technology and Tool Portability}
|
||||
|
||||
% technology overview
|
||||
OpenRAM is technology-independent by using a technology directory that
|
||||
includes the technology's specific information, rules, and library
|
||||
cells. Technology parameters such as the design rule check (DRC) rules
|
||||
and the GDS layer map are required to ensure that the dynamically
|
||||
generated designs are DRC clean. Custom designed library cells such as
|
||||
the memory cell and the sense amplifier are also placed in this
|
||||
directory. A very simple design rule parameter file has the most
|
||||
important design rules for constructing basic interconnect and
|
||||
transistor devices. FreePDK45 and SCMOS reference technologies are provided.
|
||||
|
||||
% hand-optimized cells
|
||||
OpenRAM uses some custom-designed library primitives as technology
|
||||
input. Since density is extremely important, the following cells are
|
||||
pre-designed in each technology: 6T cell, sense amplifier,
|
||||
master-slave flip-flop, tri-state gate, and write driver. All other
|
||||
cells are generated on-the-fly using parameterizable transistor and
|
||||
gate primitives.
|
||||
|
||||
% technology specific features
|
||||
OpenRAM can be used for various technologies since it creates the
|
||||
basic components of memory designs that are common over these
|
||||
technologies. For technologies that have specific design requirements,
|
||||
such as specialized well contacts, the user can include call-back
|
||||
helper functions in the technology directory. This is done so that the
|
||||
main compiler remains free of dependencies to specific technologies.
|
||||
|
||||
% DRC and LVS
|
||||
OpenRAM has two functions that provide a wrapper interface with DRC
|
||||
and LVS tools. These two functions perform DRC and LVS using the GDSII
|
||||
layout and SPICE netlist files. Since each DRC and LVS tool has
|
||||
different output, this routine is customized per tool to parse DRC/LVS
|
||||
reports and return the number of errors while also outputting debug
|
||||
information. These routines allow flexibility of any DRC/LVS tool,
|
||||
but the default implementation calls Calibre nmDRC and nmLVS. In
|
||||
OpenRAM, both DRC and LVS are performed at all levels of the design
|
||||
hierarchy to enhance bug tracking. DRC and LVS can be disabled for
|
||||
improved run-time or if tool licenses are not available.
|
||||
|
||||
\subsection{Class Hierarchy}
|
||||
|
||||
\subsubsection{High-Level Classes}
|
||||
|
||||
The {\it openram} class (openram.py) organizes execution and
|
||||
instantiates a single memory design using the {\it sram} class. It
|
||||
accepts user-provided parameters to generate the design, performs the
|
||||
optional extraction, performs characterization, and saves the
|
||||
resulting design files.
|
||||
|
||||
The {\it sram} class (sram.py) decides the appropriate internal parameter
|
||||
dependencies shown in Table~\ref{table:variables}. They are dependent
|
||||
on the user-desired data word size, number of words, and number of banks.
|
||||
It is responsible for instantiation of the single control logic module which
|
||||
controls the SRAM banks. The control logic ensures that only one bank
|
||||
is active in a given address range.
|
||||
|
||||
The {\it bank} class (bank.py) does the bulk of the non-control memory layout. It
|
||||
instantiates $1$, $2$, or $4$ bit-cell arrays and coordinates the row and column
|
||||
address decoders along with their pre-charge, sense amplifiers, and input/output
|
||||
data flops.
|
||||
|
||||
\begin{table}
|
||||
\centering
|
||||
\caption{Dependencies required for sub-modules}
|
||||
\begin{tabular}{|c|l|} \hline
|
||||
Variable&Equation \\ \hline
|
||||
\texttt{Total Bits} & $word\_size*num\_words$ \\ \hline
|
||||
\texttt{Words Per Row} & $\sqrt(num\_words)/word\_size$ \\ \hline
|
||||
\texttt{Num of Rows} & $num\_words/words\_per\_row$ \\ \hline
|
||||
\texttt{Num of Cols} & $words\_per\_row*word\_size$ \\ \hline
|
||||
\texttt{Col Addr Size} & $\log_2(words\_per\_row)$ \\ \hline
|
||||
\texttt{Row Addr Size} & $\log_2(num\_of\_rows)$ \\ \hline
|
||||
\texttt{Total Addr Size} & $row\_addr\_size + col\_addr\_size$ \\ \hline
|
||||
\texttt{Data Size} & $word\_size$ \\ \hline
|
||||
\texttt{Num of Bank} & $num\_banks$ \\ \hline
|
||||
\end{tabular}
|
||||
\label{table:variables}
|
||||
\end{table}
|
||||
|
||||
\subsubsection{Block Classes}
|
||||
|
||||
Every other block in the memory design has a class for its base cell
|
||||
(e.g., sense\_amplifier.py) and an array class (e.g.,
|
||||
sense\_amplifier\_array.py) that is responsible for tiling the base
|
||||
cell. Each class is responsible for physically placing and logically
|
||||
connecting its own sub-circuits while passing its dimensions and port
|
||||
locations up to higher-level modules.
|
||||
|
||||
\subsubsection{Low-Level Classes}
|
||||
|
||||
OpenRAM provides parameterized transistor and logic gate
|
||||
classes that help with technology portability. These classes generate
|
||||
a technology-specific transistor and simple logic gate layouts so that
|
||||
many modules do not rely on library cells. It is also used
|
||||
when a module such as the write driver needs transistor sizing
|
||||
to optimize performance. The parameterized transistor (ptx.py) generates a
|
||||
basic transistor of specified type and size. The parameterized
|
||||
transistor class is used to provide several parameterized gates
|
||||
including pinv.py, nand2.py, nand3.py, and nor2.py.
|
||||
|
||||
% FIXME
|
||||
% crude fix to preven widow Section
|
||||
%\clearpage
|
||||
\subsection{Characterization}
|
||||
|
||||
% overview
|
||||
OpenRAM includes a memory characterizer that measures the timing and
|
||||
power characteristics through SPICE simulation. The
|
||||
characterizer has four main stages: generating the SPICE stimulus,
|
||||
running the circuit simulations, parsing the simulator's output, and
|
||||
producing the characteristics in a Liberty (.lib) file.
|
||||
|
||||
% standard format of stimulus
|
||||
The stimulus is written in standard SPICE format and can be used with
|
||||
any simulator that supports this. The stimulus only uses the
|
||||
interface of the memory (e.g., bi-directional data bus, address bus,
|
||||
and control signals) to perform \enquote{black box} timing measurements.
|
||||
|
||||
% what is measured and how
|
||||
Results from simulations are used to produce the average power,
|
||||
setup/hold times, and timing delay of the memory design. Setup and
|
||||
hold times are obtained by analyzing the flip-flop library cell
|
||||
because OpenRAM uses a completely synchronous input interface. The
|
||||
setup time, hold time, and delay are found using a fast bisection
|
||||
search.
|
||||
|
||||
\subsection{Unit Tests}
|
||||
|
||||
Probably the most important feature of OpenRAM is the set of thorough
|
||||
regression tests implemented with the Python unit test framework.
|
||||
These unit tests allow users to add features and easily verifying if
|
||||
functionality is broken. The tests also work in multiple technologies
|
||||
so they can guide users when porting to new technologies. Every module
|
||||
has its own regression test and there are also regression tests for
|
||||
memory functionality, verifying library cells, timing
|
||||
characterization, and technology verification.
|
||||
|
||||
|
|
@ -1,68 +0,0 @@
|
|||
\section{Introduction}
|
||||
\label{sec:introduction}
|
||||
|
||||
% why memory compilers are important
|
||||
Static Random Access Memories (SRAMs) have become a standard component
|
||||
embedded in all System-on-Chip (SoC), Application-Specific Integrated
|
||||
Circuit (ASIC), and micro-processor designs. Their wide application
|
||||
leads to a variety of requirements in circuit design and memory
|
||||
configuration. However, manual design is
|
||||
too time consuming. The
|
||||
regular structure of memories leads well to automation that produces
|
||||
size and configuration variations quickly, but developing this with
|
||||
multiple technologies and tool methodologies is challenging. In
|
||||
addition, memory designs play a significant role in overall system
|
||||
performance and costs, so optimization is important. Thus, a memory
|
||||
compiler is a critical tool.
|
||||
|
||||
% why academics need memory compilers
|
||||
Most academic ICs design methodologies are limited by the availability
|
||||
of memories. Many standard-cell Process Design Kits (PDKs) are
|
||||
available from foundries and vendors, but these PDKs frequently do not
|
||||
come with memory arrays or memory compilers. If a memory compiler is
|
||||
freely available, it often only supports a generic process technology
|
||||
that is not fabricable. Due to academic funding restrictions,
|
||||
commercial industry solutions are often not feasible for
|
||||
researchers. In addition, these commercial solutions are limited in
|
||||
customization of the memory sizes and specific components of the
|
||||
memory. PDKs may have the options to request \enquote{black box}
|
||||
memory models, but these are also not modifiable and have limited
|
||||
available configurations. These restrictions and licensing issues make
|
||||
comparison and experimentation with real world memories impossible.
|
||||
|
||||
% manually designing is time consuming
|
||||
Academic researchers are able to design their own custom memories, but
|
||||
this can be a tedious and time-consuming task and may not be the intended
|
||||
purpose of the research. Frequently, the memory design is the bare
|
||||
minimum that the research project requires,
|
||||
and, because of this, the memory designs are often inferior and are not
|
||||
optimized. In memory research, peripheral circuits are often not
|
||||
considered when comparing memory performance and density. The
|
||||
lack of a customizable compiler makes it difficult for researchers to
|
||||
prototype and verify circuits and methodologies beyond a single row or
|
||||
column of memory cells.
|
||||
|
||||
% what are the goals of OpenRAM
|
||||
The OpenRAM project aims to provide an open-source memory compiler
|
||||
development framework for memories. It provides reference circuit and
|
||||
physical implementations in a generic $45$nm technology and fabricable
|
||||
Scalable CMOS (SCMOS), but it has also been ported to several
|
||||
commercial technology nodes using a simple technology file. OpenRAM
|
||||
also includes a characterization methodology so that it can generate
|
||||
the timing and power characterization results in addition to circuits and
|
||||
layout while remaining independent of specific commercial tools. Most
|
||||
importantly, OpenRAM is completely user-modifiable since all source
|
||||
code is open source at:
|
||||
\begin{center}
|
||||
\url{https://openram.soe.ucsc.edu/}
|
||||
\end{center}
|
||||
|
||||
The remainder of this paper is organized as follows:
|
||||
Section~\ref{sec:background} provides a background on previous memory
|
||||
compilers. Section~\ref{sec:architecture} presents the reference
|
||||
memory architecture in OpenRAM. Section~\ref{sec:implementation}
|
||||
specifically introduces the implementation and main features of the
|
||||
OpenRAM memory compiler. In Section~\ref{sec:results}, an analysis of
|
||||
the area, timing and power is shown for different sizes and
|
||||
technologies of memory. Finally, the paper is summarized in
|
||||
Section~\ref{sec:conclusions}.
|
||||
|
|
@ -1,122 +0,0 @@
|
|||
% This file should be compiled with V2.5 of "sig-alternate.cls" May 2012
|
||||
% This file has been modified by Brian Chen (bchen12@ucsc.edu) for the purpose of simplifying the sections
|
||||
%
|
||||
% This example file demonstrates the use of the 'sig-alternate.cls'
|
||||
% V2.5 LaTeX2e document class file. It is for those submitting
|
||||
% articles to ACM Conference Proceedings WHO DO NOT WISH TO
|
||||
% STRICTLY ADHERE TO THE SIGS (PUBS-BOARD-ENDORSED) STYLE.
|
||||
% The 'sig-alternate.cls' file will produce a similar-looking,
|
||||
% albeit, 'tighter' paper resulting in, invariably, fewer pages.
|
||||
%
|
||||
% ----------------------------------------------------------------------------------------------------------------
|
||||
% This .tex file (and associated .cls V2.5) produces:
|
||||
% 1) The Permission Statement
|
||||
% 2) The Conference (location) Info information
|
||||
% 3) The Copyright Line with ACM data
|
||||
% 4) NO page numbers
|
||||
%
|
||||
% as against the acm_proc_article-sp.cls file which
|
||||
% DOES NOT produce 1) thru' 3) above.
|
||||
%
|
||||
% Using 'sig-alternate.cls' you have control, however, from within
|
||||
% the source .tex file, over both the CopyrightYear
|
||||
% (defaulted to 200X) and the ACM Copyright Data
|
||||
% (defaulted to X-XXXXX-XX-X/XX/XX).
|
||||
% e.g.
|
||||
% \CopyrightYear{2007} will cause 2007 to appear in the copyright line.
|
||||
% \crdata{0-12345-67-8/90/12} will cause 0-12345-67-8/90/12 to appear in the copyright line.
|
||||
%
|
||||
% ---------------------------------------------------------------------------------------------------------------
|
||||
% This .tex source is an example which *does* use
|
||||
% the .bib file (from which the .bbl file % is produced).
|
||||
% REMEMBER HOWEVER: After having produced the .bbl file,
|
||||
% and prior to final submission, you *NEED* to 'insert'
|
||||
% your .bbl file into your source .tex file so as to provide
|
||||
% ONE 'self-contained' source file.
|
||||
%
|
||||
% ================= IF YOU HAVE QUESTIONS =======================
|
||||
% Questions regarding the SIGS styles, SIGS policies and
|
||||
% procedures, Conferences etc. should be sent to
|
||||
% Adrienne Griscti (griscti@acm.org)
|
||||
%
|
||||
% Technical questions _only_ to
|
||||
% Gerald Murray (murray@hq.acm.org)
|
||||
% ===============================================================
|
||||
%
|
||||
% For tracking purposes - this is V2.0 - May 2012
|
||||
% Custom Modified Version - November 2013
|
||||
|
||||
\documentclass{sig-alternate-05-2015}
|
||||
%\RequirePackage[pdftex]{hyperref}
|
||||
\usepackage{comment}
|
||||
\usepackage{graphicx}
|
||||
\usepackage[autostyle]{csquotes}
|
||||
\usepackage{subfigure}
|
||||
|
||||
\newcommand{\fixme}[1]{{\Large FIXME:} {\bf #1}}
|
||||
\newcommand{\todo}[1]{{\bf TODO: {#1}}\\}
|
||||
\newcommand{\note}[1]{{\bf Note:} \{#1\}\\}
|
||||
\newcommand{\comm}[1]{\small{\it{ //{#1}}}}
|
||||
|
||||
|
||||
% --- Author Metadata here ---
|
||||
\conferenceinfo{ICCAD}{International Conference on Computer-Aided Design}
|
||||
%\CopyrightYear{2007} % Allows default copyright year (20XX) to be over-ridden - IF NEED BE.
|
||||
%\crdata{0-12345-67-8/90/01} % Allows default copyright data (0-89791-88-6/97/05) to be over-ridden - IF NEED BE.
|
||||
% --- End of Author Metadata ---
|
||||
|
||||
\title{OpenRAM: An Open-Source Memory Compiler\\
|
||||
\vspace{-0.5cm}\center{\normalsize{Invited Paper}}}
|
||||
%\titlenote{Some Copyright info about OpenRAM??????}}
|
||||
|
||||
\numberofauthors{1}
|
||||
\author{
|
||||
%% TO DAC: Guthaus, Stine, Ataei, Chen, Wu, Sarwar
|
||||
\alignauthor Matthew R. Guthaus$^1$, James E. Stine$^2$, Samira Ataei$^2$, \\Brian Chen$^1$, Bin Wu$^1$, Mehedi Sarwar$^2$ \\
|
||||
\affaddr{$^1$ Department of Computer Engineering, University of California Santa Cruz, Santa Cruz, CA 95064}\\
|
||||
\affaddr\{mrg, bchen12, bwu8\}@ucsc.edu \\
|
||||
\affaddr{$^2$ Electrical and Computer Engineering Department, Oklahoma State University, Stillwater, OK 74078}\\
|
||||
\affaddr\{james.stine, ataei, mehedis\}@okstate.edu}
|
||||
|
||||
%% \alignauthor Matthew Guthaus, Brian Chen, Bin Wu \\
|
||||
%% \affaddr{Department of Computer Engineering} \\
|
||||
%% \affaddr{University of California Santa Cruz} \\
|
||||
%% \affaddr{Santa Cruz, CA 95064, USA} \\
|
||||
%% \affaddr{\{mrg,bchen12,bwu8\}@ucsc.edu}
|
||||
%% \and
|
||||
%% \alignauthor James Stine, Samira Ataei, Mehedi Sarwar \\
|
||||
%% \affaddr{Electrical and Computer Engineering Department} \\
|
||||
%% \affaddr{Oklahoma State University} \\
|
||||
%% \affaddr{Stillwater, OK 74078} \\
|
||||
%% \affaddr{\{james.stine,ataei,XXXX\}@okstate.edu}
|
||||
%%}
|
||||
|
||||
|
||||
\begin{document}
|
||||
|
||||
\CopyrightYear{2016}
|
||||
\setcopyright{acmlicensed}
|
||||
\conferenceinfo{ICCAD '16,}{November 07 - 10, 2016, Austin, TX, USA}
|
||||
\isbn{978-1-4503-4466-1/16/11}\acmPrice{\$15.00}
|
||||
\doi{http://dx.doi.org/10.1145/2966986.2980098}
|
||||
\maketitle
|
||||
|
||||
\input{abstract}
|
||||
|
||||
%\category{J.6}{COMPUTER-AIDED ENGINEERING}{\\Computer-aided design (CAD)}
|
||||
%\terms{Design, Algorithms}
|
||||
%\keywords{OpenRAM, Memory Compiler, Open-source}
|
||||
|
||||
\input{introduction}
|
||||
\input{background}
|
||||
\input{architecture}
|
||||
\input{implementation}
|
||||
\input{results}
|
||||
\input{conclusion}
|
||||
\input{acknowledgments}
|
||||
|
||||
\bibliographystyle{abbrv}
|
||||
\bibliography{references} % Create bibliography using the file: references.bib
|
||||
|
||||
%\input{appendix}
|
||||
\end{document}
|
||||
|
|
@ -1,586 +0,0 @@
|
|||
@Comment @string{DAC = "ACM/IEEE Design Automation Conference~(DAC)"}
|
||||
@Comment @string{TDEV = "IEEE Transactions on Electron Devices"}
|
||||
@Comment @string{DATE = "IEEE Design, Automation and Test in Europe~(DATE)"}
|
||||
@Comment @string{ISSCC = "IEEE International Solid-State Circuits Conference~(ISSCC)"}
|
||||
@Comment @string{TVLSI = "IEEE Transactions on Very Large Scale Integration~(VLSI) Systems"}
|
||||
@Comment @string{JSSC = "IEEE Journal of Solid-State Circuits~(JSSC)"}
|
||||
@Comment @string{ICCD = "International Conference on Computer Design~(ICCD)"}
|
||||
@Comment @string{ISLPED = "IEEE International Symposium on Low Power Electronics and Design~(ISLPED)"}
|
||||
@Comment @STRING{ICCAD = "IEEE/ACM International Conference on Computer-Aided Design~(ICCAD)"}
|
||||
@Comment @string{ASP-DAC = "IEEE Asia and South Pacific Design Automation Conference~(ASP-DAC)"}
|
||||
@Comment @string{ISCAS = "IEEE International Symposium on Circuits and Systems~(ISCAS)"}
|
||||
@Comment @string{TCAD = "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems~(TCAD)"}
|
||||
@Comment @string{GLSVLSI = "ACM Great Lakes Symposium on VLSI~(GLSVLSI)"}
|
||||
@Comment @string{TCASI = "IEEE Transactions on Circuits and Systems I~(TCAS-I)"}
|
||||
@Comment @string{TCASII = "IEEE Transactions on Circuits and Systems II~(TCAS-II)"}
|
||||
@Comment @string{TC = "IEEE Transactions on Computers"}
|
||||
@Comment @string{ISPD = "IEEE International Symposium on Physical Design~(ISPD)"}
|
||||
@Comment @string{TODAES = "ACM Transactions on Design Automation of Electronic Systems~(TODAES)"}
|
||||
@Comment @string{ISVLSI = "IEEE International Symposium on Very Large Scale Integration~(ISVLSI)"}
|
||||
@Comment @string{ISQED = "International Symposium on Quality Electronic Design~(ISQED)"}
|
||||
@Comment @string{TNUKE = "IEEE Transactions on Nuclear Science"}
|
||||
@Comment @string{MWSCAS = "IEEE Midwest Symposium on Circuits and Systems~(MWSCAS)"}
|
||||
@Comment @string{MSE = "IEEE International Conference on Microelectronic Systems Education~(MSE)"}
|
||||
|
||||
@string{DAC = "DAC"}
|
||||
@string{TDEV = "TDEV"}
|
||||
@string{DATE = "DATE"}
|
||||
@string{ISSCC = "ISSCC"}
|
||||
@string{TVLSI = "TVLSI"}
|
||||
@string{JSSC = "JSSC"}
|
||||
@string{ICCD = "ICCD"}
|
||||
@string{ISLPED = "ISLPED"}
|
||||
@STRING{ICCAD = "ICCAD"}
|
||||
@string{ASP-DAC = "ASP-DAC"}
|
||||
@string{ISCAS = "ISCAS"}
|
||||
@string{TCAD = "TCAD"}
|
||||
@string{GLSVLSI = "GLSVLSI"}
|
||||
@string{TCASI = "TCAS-I"}
|
||||
@string{TCASII = "TCAS-II"}
|
||||
@string{TC = "TCOMP"}
|
||||
@string{ISPD = "ISPD"}
|
||||
@string{TODAES = "TODAES"}
|
||||
@string{ISVLSI = "ISVLSI"}
|
||||
@string{ISQED = "ISQED"}
|
||||
@string{TNUKE = "Trans. on Nuclear Science"}
|
||||
@string{MWSCAS = "MWSCAS"}
|
||||
@string{MSE = "MSE"}
|
||||
|
||||
@book{Rabaey:2003,
|
||||
title = {Digital Integrated Circuits: A Design Perspective},
|
||||
author = {J. Rabaey and A. Chandrakasan and B. Nikolić},
|
||||
year = {2003},
|
||||
publisher = {Pearson Education, Inc.},
|
||||
edition = {2nd}
|
||||
}
|
||||
|
||||
@book{Chandrakasan:2001,
|
||||
title = {Design of High Performance Microprocessor Circuits},
|
||||
booktitle = {Design of High Performance Microprocessor Circuits},
|
||||
author = {A. Chandrakasan and W.J. Bowhill and F. Fox},
|
||||
year = {2001},
|
||||
publisher = {IEEE Press}
|
||||
}
|
||||
|
||||
@manual{gdsmill,
|
||||
title = {GDS Mill User Manual},
|
||||
author = {M. Wieckowski},
|
||||
year = {2010}
|
||||
}
|
||||
|
||||
%these are end of chapter references from Rabaey
|
||||
%%%%%%%%%%%
|
||||
@article{Amrutur:2001,
|
||||
author = {B.S. Amrutur and M.A. Horowitz},
|
||||
journal = JSSC,
|
||||
title = {Fast Low-Power Decoders for RAMs},
|
||||
number = {10},
|
||||
pages = {1506-1515},
|
||||
volume = {36},
|
||||
year = {2001},
|
||||
month = {Oct}
|
||||
}
|
||||
|
||||
@inbook{Preston:2001,
|
||||
title = {Register Files and Caches},
|
||||
author = {R.P. Preston},
|
||||
crossref = {Chandrakasan:2001}
|
||||
}
|
||||
|
||||
@book{Itoh:2001,
|
||||
title = {VLSI Memory Chip Design},
|
||||
author = {K. Itoh},
|
||||
publisher = {Springer-Verlag},
|
||||
year = {2001}
|
||||
}
|
||||
|
||||
@article{Itoh:1990,
|
||||
author = {K. Itoh},
|
||||
journal = JSSC,
|
||||
title = {Trends in Megabit DRAM Circuit Design},
|
||||
number = {3},
|
||||
pages = {778-798},
|
||||
volume = {25},
|
||||
year = {1990},
|
||||
month = {Jun}
|
||||
}
|
||||
|
||||
@article{May:1979,
|
||||
author = {T. May and M. Woods},
|
||||
journal = TDEV,
|
||||
title = {Aplha-Particle-Induced Soft Errors in Dynamic Memories},
|
||||
number = {1},
|
||||
pages = {2-9},
|
||||
volume = {26},
|
||||
year = {1979},
|
||||
month = {Jan}
|
||||
}
|
||||
|
||||
@ARTICLE{Tosaka:1997,
|
||||
author={Y. Tosaka and S. Satoh and T. Itakura and K. Suzuki and T. Sugii and H. Ehara and G.A. Woffinden},
|
||||
journal=TDEV,
|
||||
title={Cosmic Ray Neutron-Induced Soft Errors in Sub-Half Micron CMOS Circuits},
|
||||
year={1997},
|
||||
volume={18},
|
||||
number={3},
|
||||
pages={99-101}
|
||||
}
|
||||
|
||||
@ARTICLE{Regitz:1970,
|
||||
author={W.M. Regitz and J. Karp},
|
||||
journal=JSSC,
|
||||
title={Three-transistor-cell 1024-bit 500-ns MOS RAM},
|
||||
year={1970},
|
||||
volume={5},
|
||||
number={5},
|
||||
pages={181-186}
|
||||
}
|
||||
|
||||
@INPROCEEDINGS{Kim1:2011,
|
||||
author={S. Kim and M. Guthaus},
|
||||
booktitle=DAC,
|
||||
title={Leakage-aware redundancy for reliable sub-threshold memories},
|
||||
year={2011},
|
||||
pages={435-440}
|
||||
}
|
||||
|
||||
@INPROCEEDINGS{Kim2:2011,
|
||||
author={S. Kim and M. Guthaus},
|
||||
booktitle=VLSISOC,
|
||||
title={SNM-aware power reduction and reliability improvement in 45nm {SRAM}s},
|
||||
year={2011},
|
||||
pages={204-207}
|
||||
}
|
||||
|
||||
@INPROCEEDINGS{Kim3:2011,
|
||||
author={S. Kim and M. Guthaus},
|
||||
booktitle=ICCAD,
|
||||
title={Low-power multiple-bit upset tolerant memory optimization},
|
||||
year={2011},
|
||||
pages={577-581}
|
||||
}
|
||||
|
||||
@INPROCEEDINGS{Kim:2012,
|
||||
author={S. Kim and M. Guthaus},
|
||||
booktitle=VLSISOC,
|
||||
title={Dynamic voltage scaling for SEU-tolerance in low-power memories},
|
||||
year={2012},
|
||||
pages={207-212}
|
||||
}
|
||||
|
||||
|
||||
@ARTICLE{Rusu:2003,
|
||||
author={S. Rusu and J. Stinson and S. Tam and J. Leung and H. Muljono and B. Cherkauer},
|
||||
journal=JSSC,
|
||||
title={A 1.5-GHz 130-nm Itanium reg; 2 Processor with 6-MB on-die L3 cache},
|
||||
year={2003},
|
||||
volume={38},
|
||||
number={11},
|
||||
pages={1887-1895}
|
||||
}
|
||||
|
||||
@article{itrs:2012,
|
||||
author = {International Technology Roadmap for Semiconductors},
|
||||
title = {2012 ITRS Report: System Drivers},
|
||||
howpublished = {www.itrs.net},
|
||||
year = {2012}
|
||||
}
|
||||
|
||||
@article{Kurdahi:2006,
|
||||
author = {F.J. Kurdahi and A.M. Eltawil and Y.H. Park and R.N Kanj and S.R. Nassif},
|
||||
journal = ISQED,
|
||||
title = {System-level {SRAM} Yield Enhancement},
|
||||
year = {2006},
|
||||
month = {Mar}
|
||||
}
|
||||
|
||||
|
||||
@misc{i7:2011,
|
||||
author = {A. Shimpi},
|
||||
title = {Intel Core i7 3960X (Sandy Bridge) Review: Keeping the High-End Alive},
|
||||
howpublished = {\url{http://www.anandtech.com/show/5091/intel-core-i7-3960x-sandy-bridge-e-review-keeping-the-high-end-alive}},
|
||||
year = {2011},
|
||||
month = {Nov}
|
||||
}
|
||||
|
||||
|
||||
|
||||
@misc{calibre:2013,
|
||||
author = {Mentor Graphics},
|
||||
title = {Calibre nmDRC and nmLVS},
|
||||
howpublished = {\url{http://www.mentor.com/products/ic_nanometer_design/verification-signoff/physical-verification/}},
|
||||
year = {2013}
|
||||
}
|
||||
|
||||
@misc{hspice:2013,
|
||||
author = {Synopsis},
|
||||
title = {HSPICE},
|
||||
howpublished = {\url{http://www.synopsys.com/tools/Verification/AMSVerification/CircuitSimulation/HSPICE/Pages/default.aspx}},
|
||||
year = {2013}
|
||||
}
|
||||
|
||||
@INPROCEEDINGS{Athe:2009,
|
||||
author={P. Athe and S. Dasgupta},
|
||||
booktitle={{ISIEA}},
|
||||
title={A comparative study of 6T, 8T and 9T decanano {SRAM} cell},
|
||||
year={2009},
|
||||
volume={2},
|
||||
pages={889-894}
|
||||
}
|
||||
|
||||
@ARTICLE{Calin:1996,
|
||||
author={T. Calin and M. Nicolaidis and R. Velazco},
|
||||
journal=TNUKE,
|
||||
title={Upset hardened memory design for submicron CMOS technology},
|
||||
year={1996},
|
||||
volume={43},
|
||||
number={6},
|
||||
pages={2874-2878}
|
||||
}
|
||||
|
||||
@INPROCEEDINGS{Jung:2012,
|
||||
author={I. Jung and Y. Kim and F. Lombardi},
|
||||
booktitle=MWSCAS,
|
||||
title={A novel sort error hardened 10T {SRAM} cells for low voltage operation},
|
||||
year={2012},
|
||||
pages={714-717}
|
||||
}
|
||||
|
||||
@ARTICLE{Goudarzi:2010,
|
||||
author={M. Goudarzi and T. Ishihara},
|
||||
journal=TVLSI,
|
||||
title={{SRAM} Leakage Reduction by Row/Column Redundancy Under Random Within-Die Delay Variation},
|
||||
year={2010},
|
||||
volume={18},
|
||||
number={12},
|
||||
pages={1660-1671}
|
||||
}
|
||||
|
||||
@techreport{ibm:1997,
|
||||
author = {IBM},
|
||||
title = {Understanding Static RAM Operation},
|
||||
howpublished = {IBM Applications Note},
|
||||
year = {1997},
|
||||
month = {Mar}
|
||||
}
|
||||
|
||||
|
||||
@misc{python:2013,
|
||||
author = {Python},
|
||||
title = {The Python Programming Language},
|
||||
howpublished = {\url{http://www.python.org}},
|
||||
year = {2013}
|
||||
}
|
||||
|
||||
|
||||
@misc{Wieckowski:2010,
|
||||
author = {Michael Wieckowski},
|
||||
title = {GDS Mill},
|
||||
howpublished = {\url{http://michaelwieckowski.com/?page_id=190}},
|
||||
year = {2010}
|
||||
}
|
||||
|
||||
@misc{globalfoundries:2015,
|
||||
author = {{Global Foundries}},
|
||||
title = {{ASICs}},
|
||||
howpublished = {\url{http://www.globalfoundries.com/technology-solutions/asics}},
|
||||
year = {2015}
|
||||
}
|
||||
|
||||
@misc{synopsys:2015,
|
||||
author = {Synopsys},
|
||||
title = {DesignWare Memory Compilers},
|
||||
howpublished = {\url{http://www.synopsys.com/dw/ipdir.php?ds=dwc_sram_memory_compilers}},
|
||||
year = {2015}
|
||||
}
|
||||
|
||||
@misc{dolphin:2015,
|
||||
author = {{Dolphin Technology}},
|
||||
title = {Memory Products},
|
||||
howpublished = {\url{http://www.dolphin-ic.com/memory-products.html}},
|
||||
year = {2015}
|
||||
}
|
||||
|
||||
@misc{faraday:2015,
|
||||
author = {{Faraday Technologies}},
|
||||
title = {Memory Compiler Architecture},
|
||||
howpublished = {\url{http://www.faraday-tech.com/html/Product/IPProduct/LibraryMemoryCompiler/index.htm}},
|
||||
year = {2015}
|
||||
}
|
||||
|
||||
@misc{arm:2015,
|
||||
author = {ARM},
|
||||
title = {Embedded Memory {IP}},
|
||||
howpublished = {\url{http://www.arm.com/products/physical-ip/embedded-memory-ip/index.php}},
|
||||
year = {2015}
|
||||
}
|
||||
|
||||
|
||||
@misc{scmos,
|
||||
author = {MOSIS},
|
||||
title = {{MOSIS} Scalable {CMOS} ({SCMOS})},
|
||||
howpublished = {\url{https://www.mosis.com/files/scmos/scmos.pdf}},
|
||||
year = {2015}
|
||||
}
|
||||
|
||||
%%%look at this paper
|
||||
@article{Hanson:2008,
|
||||
author = {S. Hanson and M. Seok and D. Sylvester and D. Blaauw},
|
||||
journal = TDEV,
|
||||
title = {Nanometer device scaling in subthreshold logic and {SRAM}},
|
||||
number = {1},
|
||||
pages = {175-185},
|
||||
volume = {55},
|
||||
year = {2008}
|
||||
}
|
||||
|
||||
%%%look at this paper
|
||||
@article{Baeg:2009,
|
||||
author={S. Baeg and S. Wen and R. Wong},
|
||||
journal=TNUKE,
|
||||
title={{SRAM} Interleaving Distance Selection With a Soft Error Failure Model},
|
||||
year={2009},
|
||||
month={Aug.},
|
||||
volume={56},
|
||||
number={4},
|
||||
pages={2111-2118}
|
||||
}
|
||||
|
||||
%%%look at this paper
|
||||
@article{Amrutur:2001,
|
||||
author={B. Amrutur and M. Horowitz},
|
||||
journal=JSSC,
|
||||
title={Fast low-power decoders for {RAMs}},
|
||||
year={2001},
|
||||
month={Oct},
|
||||
volume={36},
|
||||
number={10},
|
||||
pages={1506-1515}
|
||||
}
|
||||
|
||||
@inproceedings{Chen:2012,
|
||||
author={Chen Ming and Bai Na},
|
||||
booktitle={{CyberC}},
|
||||
title={An Efficient and Flexible Embedded Memory {IP} Compiler},
|
||||
year={2012},
|
||||
month={Oct},
|
||||
pages={268-273},
|
||||
keywords={SRAM chips;embedded systems;interpolation;polynomials;circuit structure;efficient embedded memory IP compiler;flexible embedded memory IP compiler;polynomial interpolation algorithm;single-port SRAM compiler;Integrated circuit modeling;Interpolation;Mathematical model;Memory management;Random access memory;Tiles;Timing;SRAM;interpolation;memory compiler;modeling;tiling},
|
||||
doi={10.1109/CyberC.2012.52}
|
||||
}
|
||||
|
||||
@inproceedings{Wu:2010,
|
||||
author={Sheng Wu and Xiang Zheng and Zhiqiang Gao and Xiangqing He},
|
||||
booktitle={{DDECS}},
|
||||
title={A 65nm embedded low power {SRAM} compiler},
|
||||
year={2010},
|
||||
month={April},
|
||||
pages={123-124},
|
||||
keywords={CMOS technology;Design methodology;Helium;Kernel;Layout;Libraries;Microelectronics;Program processors;Random access memory;SRAM chips;SRAM compiler;SoC IP;low power},
|
||||
doi={10.1109/DDECS.2010.5491802}
|
||||
}
|
||||
|
||||
@inproceedings{Xu:2007,
|
||||
author={Yi Xu and Zhiqiang Gao and Xiangqing He},
|
||||
booktitle=ISCAS,
|
||||
title={A Flexible Embedded {SRAM} {IP} Compiler},
|
||||
year={2007},
|
||||
month={May},
|
||||
pages={3756-3759},
|
||||
keywords={SRAM chips;circuit layout CAD;elemental semiconductors;embedded systems;logic design;program compilers;silicon;Si;atatic random access memory;block assembly techniques;embedded SRAM IP compiler;physical data syntax;silicon compiler;Assembly;Capacitance;Circuits;Energy consumption;Graphical user interfaces;Helium;Microelectronics;Random access memory;SRAM chips;Silicon compiler},
|
||||
doi={10.1109/ISCAS.2007.378778}
|
||||
}
|
||||
|
||||
%%%%Newest memory compiler on market in 2014
|
||||
@inproceedings{Goldman:2014,
|
||||
author={Goldman, R. and Bartleson, K. and Wood, T. and Melikyan, V. and Babayan, E.},
|
||||
booktitle={{EWME}},
|
||||
title={Synopsys' Educational Generic Memory Compiler},
|
||||
year={2014},
|
||||
month={May},
|
||||
pages={89-92},
|
||||
keywords={SRAM chips;courseware;electronic engineering computing;electronic engineering education;GMC software tool;Synopsys educational generic memory compiler software tool;automatic SRAM cell generation;automatic static RAM cell generation;educational designs;educational process;intellectual property restrictions;Educational institutions;Layout;Memory management;Multiplexing;Ports (Computers);Random access memory;Software},
|
||||
doi={10.1109/EWME.2014.6877402}
|
||||
}
|
||||
|
||||
@mastersthesis{butera:2013,
|
||||
author = {J. Butera},
|
||||
title = {OpenRAM: An Open-Source Memory Compiler},
|
||||
school = {University of California - Santa Cruz},
|
||||
year = {2013}
|
||||
}
|
||||
|
||||
@inproceedings{johannsen:blocks,
|
||||
author = {D. Jahannsen},
|
||||
title = {Bristle Blocks: A Silicon Compiler},
|
||||
booktitle = DAC,
|
||||
pages = {195-198},
|
||||
year = {1979}
|
||||
}
|
||||
|
||||
@book{broderson:sicompiler,
|
||||
author = {R. Broderson},
|
||||
title = {Anatomy of a Silicon Compiler},
|
||||
publisher = {Springer},
|
||||
year = {1992}
|
||||
}
|
||||
|
||||
@inproceedings{poechmueller:array,
|
||||
author = {P. Poechmueller and G.~K. Sharma and M. Glesner},
|
||||
title = {A {CAD} Tool for Designing Large, Fault-Tolerant {VLSI} Arrays},
|
||||
booktitle = GLSVLSI,
|
||||
year = {1991}
|
||||
}
|
||||
|
||||
@inproceedings{huang:array,
|
||||
author = {T.-H. Huang and C.-M. Liu and C.-W. Jen},
|
||||
title = {A High-Level Synthesizer for {VLSI} Array Architectures Dedicated to Digital Signal Processing},
|
||||
booktitle = {International Conference on Acoustics, Speech and Signal Processing},
|
||||
pages = {1221-1224},
|
||||
year = {1991}
|
||||
}
|
||||
|
||||
|
||||
@article{cabe:flexible,
|
||||
author = {AC Cabe and Z Qi and W Huang and Y Zhang and MR Stan and GS Rose},
|
||||
journal = {Cadence CDNLive},
|
||||
title = {A flexible, technology adaptive memory generation tool},
|
||||
year = {2006},
|
||||
}
|
||||
|
||||
@mastersthesis{fabmem:2010,
|
||||
author = {T. Shah},
|
||||
title = {{FabMem}: A Multiported {RAM} and {CAM} Compiler for Superscalar Design Space Exploration},
|
||||
school = {North Carolina State University},
|
||||
year = {2010}
|
||||
}
|
||||
|
||||
@misc{virage:2015,
|
||||
author = {{Virage Logic}},
|
||||
title = {{SiWare} Memory},
|
||||
howpublished = {\url{http://www.viragelogic.com}},
|
||||
year = {2015}
|
||||
}
|
||||
|
||||
|
||||
@article{RBL:1998,
|
||||
author = {B. S. Amrutur and M. A. Horowitz},
|
||||
journal = JSSC,
|
||||
title = {A Replica Technique for Wordline and Sense Control in Low-Power {SRAM}s},
|
||||
number = {8},
|
||||
pages = {1208-1219},
|
||||
volume = {33},
|
||||
year = {1998},
|
||||
month = {Aug}
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
% references for bit-density comparison
|
||||
|
||||
|
||||
@article{Bit_Density_1,
|
||||
author = {K. Kushida and others},
|
||||
journal = JSSC,
|
||||
title = {A 0.7 {V} Single-Supply {SRAM} With 0.495 $um^2$ Cell in 65 nm Technology Utilizing Self-Write-Back Sense Amplifier and Cascaded Bit Line Scheme},
|
||||
number = {4},
|
||||
pages = {1192-1198},
|
||||
volume = {44},
|
||||
year = {2009},
|
||||
month = {Apr}
|
||||
}
|
||||
|
||||
|
||||
@article{Bit_Density_2,
|
||||
author = {Sh. Miyano and others},
|
||||
journal = JSSC,
|
||||
title = {Highly Energy-Efficient {SRAM} With Hierarchical Bit Line Charge-Sharing Method Using Non-Selected Bit Line Charges},
|
||||
number = {4},
|
||||
pages = {924-931},
|
||||
volume = {48},
|
||||
year = {2013},
|
||||
month = {Apr}
|
||||
}
|
||||
|
||||
@article{Bit_Density_3,
|
||||
author = {S. O. Toh and Zh. Guo and T. K. Liu and B. Nikolic},
|
||||
journal = JSSC,
|
||||
title = {Characterization of Dynamic {SRAM} Stability in 45 nm {CMOS}},
|
||||
number = {11},
|
||||
pages = {2702-2712},
|
||||
volume = {46},
|
||||
year = {2011},
|
||||
month = {Nov}
|
||||
}
|
||||
|
||||
@article{Bit_Density_4,
|
||||
author = {K. Yamaguchi and others},
|
||||
journal = JSSC,
|
||||
title = {A 1.5-ns Access Time, 78- $um^2$ Memory-Cell Size, 64-kb {ECL-CMOS SRAM}},
|
||||
number = {2},
|
||||
pages = {167-174},
|
||||
volume = {27},
|
||||
year = {1992},
|
||||
month = {Feb}
|
||||
}
|
||||
|
||||
@article{Bit_Density_5,
|
||||
author = {N. Shibata and H. Morimura and M. Watanabe},
|
||||
journal = JSSC,
|
||||
title = {A {1-V}, {10-MHz}, 3.5-mW, {1-Mb} {MTCMOS SRAM} with Charge-Recycling Input/Output Buffers},
|
||||
number = {6},
|
||||
pages = {866-877},
|
||||
volume = {34},
|
||||
year = {1999},
|
||||
month = {Jun}
|
||||
}
|
||||
|
||||
@article{Bit_Density_6,
|
||||
author = {N. Tamba and others},
|
||||
journal = JSSC,
|
||||
title = {A 1.5-ns 256-kb {BiCMOS SRAM} with 60-ps 11-K Logic Gates},
|
||||
number = {11},
|
||||
pages = {1344-1352},
|
||||
volume = {48},
|
||||
year = {1994},
|
||||
month = {Nov}
|
||||
}
|
||||
|
||||
%author={Yamaguchi, K. and Nambu, H. and Kanetani, K. and Idei, Y. and Homma, N. and Hiramoto, T. and Tamba, N. and Watanabe, K. and Odaka, Masanori and Ikeda, T. and Ohhata, K. and Sakurai, Y.},
|
||||
@ARTICLE{127339,
|
||||
author={Yamaguchi, K. and others},
|
||||
journal=JSSC,
|
||||
title={A $1.5$-ns access time, $78~um^2$ memory-cell size, $64$-kb {ECL-CMOS SRAM}},
|
||||
year={1992},
|
||||
volume={27},
|
||||
number={2},
|
||||
pages={167-174},
|
||||
doi={10.1109/4.127339},
|
||||
ISSN={0018-9200},
|
||||
month={Feb},
|
||||
}
|
||||
|
||||
%author={Kushida, K. and Suzuki, A. and Fukano, G. and Kawasumi, A. and Hirabayashi, O. and Takeyama, Y. and Sasaki, T. and Katayama, A. and Fujimura, Y. and Yabe, T.},
|
||||
@INPROCEEDINGS{4585946,
|
||||
author={Kushida, K. and others},
|
||||
booktitle=ISVLSI,
|
||||
title={A $0.7$V single-supply {SRAM} with $0.495~um^2$ cell in $65$nm technology
|
||||
utilizing self-write-back sense amplifier and cascaded bit
|
||||
line scheme},
|
||||
year={2008},
|
||||
pages={46-47},
|
||||
doi={10.1109/VLSIC.2008.4585946},
|
||||
month={June}
|
||||
}
|
||||
|
||||
%author={Stine, J.E. and Castellanos, I. and Wood, M. and Henson, J. and Love, F. and Davis, W.R. and Franzon, P.D. and Bucher, M. and Basavarajaiah, S. and Julie Oh and Jenkal, R.},
|
||||
@INPROCEEDINGS{4231502,
|
||||
author={J. E. Stine and others},
|
||||
booktitle=MSE,
|
||||
title={{FreePDK}: An Open-Source Variation-Aware Design Kit},
|
||||
year={2007},
|
||||
pages={173-174},
|
||||
doi={10.1109/MSE.2007.44},
|
||||
month={June}
|
||||
}
|
||||
|
|
@ -1,115 +0,0 @@
|
|||
\section{Results}
|
||||
\label{sec:results}
|
||||
|
||||
Figure~\ref{fig:layout} shows several different SRAM layouts
|
||||
generated by OpenRAM in FreePDK45. OpenRAM can generate single
|
||||
bank and multi-bank SRAM arrays. Banks are
|
||||
symmetrically placed to have the same delay for data and address
|
||||
while sharing peripheral blocks such as decoders.
|
||||
\begin{figure}[tb]
|
||||
\centering
|
||||
\includegraphics[scale=.4]{./figs/layout.pdf}
|
||||
\caption{Single bank and multi-bank SRAMs (not to scale) use
|
||||
symmetrical bank placement to share peripheral circuitry and
|
||||
equalize signal delays.}
|
||||
\label{fig:layout}
|
||||
\end{figure}
|
||||
|
||||
Figure~\ref{fig:density_figure} shows the memory area of different
|
||||
total size and data word width memories in both FreePDK45 and
|
||||
SCMOS. As expected, the smaller process technology (45nm) has lower
|
||||
total area overall but the trends are similar in both technologies.
|
||||
|
||||
Figure~\ref{fig:density_figure} also shows the access time of
|
||||
different size and data word width in FreePDK45 and SCMOS. Increasing
|
||||
the memory size generally increases the access time; long bit-lines
|
||||
and word-lines increase the access time by adding more parasitic
|
||||
capacitance and resistance. Since OpenRAM uses multiple banks and
|
||||
column muxing, it is possible to have a smaller access time for larger
|
||||
memory designs, but this will sacrifice density.
|
||||
|
||||
\begin{figure}[tb]
|
||||
\begin{center}
|
||||
\centering
|
||||
%\includegraphics[width=8.5cm]{./figs/Results.pdf}
|
||||
\includegraphics[width=7.5cm , height=14cm]{./figs/Results2.pdf}
|
||||
% \subfigure[FreePDK45 memory area \label{fig:freepdk_area}]{
|
||||
% \includegraphics[scale=1]{./figs/Freepdk_Area.pdf}}
|
||||
% \subfigure[SCMOS memory area \label{fig:scn3me_area}]{
|
||||
% \includegraphics[scale=.5]{./figs/Scn3me_Area.pdf}}
|
||||
\caption{OpenRAM provides high-density memories in multiple
|
||||
technologies and sizes with corresponding characterized
|
||||
delays. \label{fig:density_figure}}
|
||||
\vspace{-0.5cm}
|
||||
\end{center}
|
||||
\end{figure}
|
||||
|
||||
%Table~\ref{table:bit-density-comparison} shows a comparison between bit
|
||||
%density of OpenRAM's generated memory designs and other publications
|
||||
%which are close in technology node with FreePDK45 and SCMOS. As shown
|
||||
%in this table, OpenRAM provides very dense SRAM arrays in both technologies.
|
||||
|
||||
\begin{table}[t]
|
||||
\centering
|
||||
\caption{OpenRAM has high density compared to other published memories in
|
||||
similar technologies.}
|
||||
\begin{tabular}{|c|c|c|c|l|l|l|l|l|} \hline
|
||||
\texttt{Ref.} & \texttt{Feature} & \texttt{Tech.} & \texttt{Density} \\
|
||||
& \texttt{Size} & & [Mb/$mm^2$] \\
|
||||
\hline \hline
|
||||
$~\cite{4585946}$ & $65$ nm & CMOS & $0.7700$ \\ \hline
|
||||
$~\cite{Bit_Density_3}$ & $45$ nm & CMOS & $0.3300$ \\ \hline
|
||||
$~\cite{Bit_Density_2}$ & $40$ nm & CMOS & $0.9400$ \\ \hline
|
||||
\verb+OpenRAM+ & $45$ nm & FreePDK45 & $0.8260$ \\ \hline \hline
|
||||
$~\cite{127339}$ & $0.5$ um & CMOS & $0.0036$ \\ \hline
|
||||
$~\cite{Bit_Density_6}$ & $0.5$ um & BiCMOS & $0.0020$ \\ \hline
|
||||
$~\cite{Bit_Density_5}$ & $0.5$ um & CMOS & $0.0050$ \\ \hline
|
||||
\verb+OpenRAM+ & $0.5$ um & SCMOS & $0.0050$ \\ \hline
|
||||
\end{tabular}
|
||||
\label{table:bit-density-comparison}
|
||||
\end{table}
|
||||
|
||||
%\begin{table*}
|
||||
%\centering
|
||||
%\caption{OpenRAM has high density, fast access time and low power consumption compared to other published memories in similar technologies.}
|
||||
%\begin{tabular}{|c|l|l|l|l|l|l|l|l|} \hline
|
||||
%\texttt{Reference} & \texttt{Technology} & \texttt{Density (Mb/$mm^2$)}& \texttt{Access time (ns)}& \texttt{Power consumption} \\ \hline \hline
|
||||
%$~\cite{Bit_Density_1}$ & $65 nm CMOS$ & $0.77$ & $28$ & $22$ $uW/MHz$ \\ \hline
|
||||
%$~\cite{Bit_Density_2}$ & $40 nm CMOS$ & $0.94$ & $45$ & $13.8$ $pJ/access/Mbit$ \\ \hline
|
||||
%$OpenRAM$ & $45 nm FreePDK45$ & $0.826$ & $9.86$ & $13.14$ $mW$ \\ \hline \hline
|
||||
%$~\cite{Bit_Density_4}$ & $0.5 um CMOS$ & $0.0036$ & $1.5$ & $6$ $W$ \\ \hline
|
||||
%$~\cite{Bit_Density_6}$ & $0.5 um BiCMOS$ & $0.002$ & $1.5$ & $35$ $W$ \\ \hline
|
||||
%$~\cite{Bit_Density_5}$ & $0.5 um CMOS$ & $0.005$ & $75$ & $3.9$ $mW$ \\ \hline
|
||||
%$OpenRAM$ & $0.5 um SCMOS$ & $0.005$ & $44.9$ & $115$ $mW$ \\ \hline
|
||||
%\end{tabular}
|
||||
%\label{table:bit-density-comparison}
|
||||
%\end{table*}
|
||||
|
||||
Comparison of power consumption and read access time of different
|
||||
memories is a bit more complicated to make a conclusion, because there
|
||||
are many trade-offs. Power and performance are highly dependent on
|
||||
circuit style (CMOS, ECL, etc.), memory organization (more banks is
|
||||
faster but sacrifices density), and the optimization goal: low-power
|
||||
or high-performance. In general, OpenRAM has reasonable trade-off
|
||||
between the two and can be customized by using an alternate sense
|
||||
amplifiers, decoders, or overall dimensional organization.
|
||||
Table~\ref{table:bit-density-comparison} compares the bit-density of
|
||||
OpenRAM against published designs using similar technology nodes. The
|
||||
results show the benefit of technology scaling and that OpenRAM has
|
||||
very good density in both technologies. As a comparison, a 76ns SRAM
|
||||
consumes 3.9mW~\cite{Bit_Density_5} while OpenRAM is much faster at
|
||||
44.9ns but consumes 115mW for the same size.
|
||||
|
||||
%Table~\ref{table:bit-density-comparison} shows a comparison between bit density, access
|
||||
%time and power consumption of OpenRAM’s generated mem-
|
||||
%ory designs and other publications which are close in tech-
|
||||
%nology node with FreePDK45 and SCMOS. As shown in this
|
||||
%table, OpenRAM provides very dense SRAM arrays in both
|
||||
%technologies. There is no easy comparison on power con-
|
||||
%sumption and read access time as these values vary with the
|
||||
%array size and configuration. Therefore, we only try to com-
|
||||
%pare the features of each work from a more general point of
|
||||
%view.
|
||||
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,16 +0,0 @@
|
|||
#!/bin/sh
|
||||
# This is a short script to simplify generating a PDF document from LaTeX and BibTeX code.
|
||||
# The script cleans plausibly existing files, generates the PDF, then cleans furthur generated files.
|
||||
|
||||
# Clean any latent files.
|
||||
rm -rf *.aux *.bbl *.blg *.log #*.pdf
|
||||
|
||||
# Generate the actual output.
|
||||
pdflatex main.tex
|
||||
bibtex main.aux
|
||||
pdflatex main.tex
|
||||
pdflatex main.tex
|
||||
mv main.pdf openram.pdf
|
||||
|
||||
# Clean all the generated files except for the .pdf
|
||||
rm -rf *.aux *.bbl *.blg *.log *.lof *.lot *.out *.toc
|
||||
Loading…
Reference in New Issue