Accidentally committed to master. Merge branch 'master' into dev

README.md

@@ -131,27 +131,34 @@ This is where simulations and DRC/LVS get run so there is no network
 traffic. The directory name is unique for each person and run of
 OpenRAM to not clobber any files and allow simultaneous runs. If it
 passes, the files are deleted. If it fails, you will see these files:
-* _calibreDRC.rul_ is the DRC rule file.
-* dc_runset is the command file for caliber.
 * temp.gds is the layout
-* test1.drc.err is the std err output of the command
+* (.mag files if using SCMOS)
-* test1.drc.out is the standard output of the command
+* temp.sp is the netlist
-* test1.drc.db is the DRC results file
+* test1.drc.err is the std err output of the DRC command
+* test1.drc.out is the standard output of the DRC command
+* test1.drc.results is the DRC results file
+* test1.lvs.err is the std err output of the LVS command
+* test1.lvs.out is the standard output of the LVS command
+* test1.lvs.results is the DRC results file
+
+Depending on your DRC/LVS tools, there will also be:
+* _calibreDRC.rul_ is the DRC rule file (Calibre)
+* dc_runset is the command file (Calibre)
+* extracted.sp (Calibre)
+* run_lvs.sh is a Netgen script for LVS (Netgen)
+* run_drc.sh is a Magic script for DRC (Magic)
+* <topcell>.spice (Magic)
 
 If DRC/LVS fails, the first thing is to check if it ran in the .out and
 .err file. This shows the standard output and error output from
 running DRC/LVS. If there is a setup problem it will be shown here.
 
-If DRC/LVS runs, but doesn't pass, you then should look at the .db
+If DRC/LVS runs, but doesn't pass, you then should look at the .results
 file. If the DRC fails, it will typically show you the command that was used
-to run caliber. It is something like this:
+to run Calibre or Magic+Netgen. 
-```
+
-  calibre -gui -drc /tmp/openram_mrg_28781_temp/drc_runset -batch 2>
+To debug, you will need a layout viewer. I prefer to use Glade 
-  /tmp/openram_mrg_28781_temp/test1.drc.err 1>
+on my Mac, but you can also use Calibre, Magic, etc. 
-  /tmp/openram_mrg_28781_temp/test1.drc.out
-```
-To debug, you will need a layout viewer. I prefer to use glade on my
-Mac, but you can also use Calibre, Magic, etc. 
 
 1. Calibre
 
@@ -195,12 +202,19 @@ ui().importCds("default",
    between processes, you have to change the importCds command (or you
    can manually run the command each time you start glade).
 
-   To load the errors, you simply do Verify->Import Caliber Errors select
+   To load the errors, you simply do Verify->Import Calibre Errors select
-   the .db file from calibre.
+   the .results file from Calibre.
 
-3. It is possible to use other viewers as well, such as:
+3. Magic
+
+   Magic is only supported in SCMOS. You will need to install the MOSIS SCMOS rules
+   and Magic from: http://opencircuitdesign.com/
+
+   When running DRC or extraction, OpenRAM will load the GDS file, save
+   the .ext/.mag files, and export an extracted netlist (.spice).
+
+4. It is possible to use other viewers as well, such as:
    * LayoutEditor http://www.layouteditor.net/ 
-   * Magic http://opencircuitdesign.com/magic/
 
 
 # Example to output/input .gds layout files from/to Cadence

compiler/hierarchy_layout.py

@@ -308,7 +308,7 @@ class layout(lef.lef):
         path.path(obj=self,
                   layer=layer, 
                   position_list=coordinates, 
-                  width=drc["minwidth_{}".format(layer)])
+                  width=width)
 
     def add_route(self, design, layers, coordinates):
         """Connects a routing path on given layer,coordinates,width. The

compiler/path.py

@@ -92,7 +92,8 @@ class path():
                 self.add_line(layer_name=self.layer_name,
                               length=abs(line_length),
                               offset=offset,
-                              orientation="horizontal")
+                              orientation="horizontal",
+                              layer_width=self.layer_width)
             # if we have y motion
             elif pl[index][1] != pl[index + 1][1]:
                 line_length = pl[index + 1][1] - pl[index][1]
@@ -104,15 +105,15 @@ class path():
                 self.add_line(layer_name=self.layer_name,
                               length=abs(line_length),
                               offset=offset,
-                              orientation="vertical")
+                              orientation="vertical",
+                              layer_width=self.layer_width)
 
-    def add_line(self, layer_name, length, offset, orientation):
+    def add_line(self, layer_name, length, offset, orientation, layer_width):
         """
         straight line object with layer_minwidth 
         (orientation: "vertical" or "horizontal") default is vertical
         """
 
-        layer_width = drc["minwidth_{0}".format(layer_name)]
         width = layer_width
         height = length 
 

compiler/wire.py

@@ -83,7 +83,8 @@ class wire(path):
                 self.add_line(layer_name=self.horiz_layer_name,
                               length=abs(line_length),
                               offset=temp_offset,
-                              orientation="horizontal")
+                              orientation="horizontal",
+                              layer_width=self.horiz_layer_width)
             elif pl[index][1] != pl[index + 1][1]:
                 line_length = pl[index + 1][1] - pl[index][1]
                 temp_offset = [pl[index][0] - 0.5 * self.vert_layer_width,
@@ -94,7 +95,8 @@ class wire(path):
                 self.add_line(layer_name=self.vert_layer_name,
                               length=abs(line_length),
                               offset=temp_offset,
-                              orientation="vertical")
+                              orientation="vertical",
+                              layer_width=self.vert_layer_width)
 
     def assert_node(self, A, B):
         """ Check if the node movements are not big enough for the