diff --git a/compiler/characterizer/trim_spice.py b/compiler/characterizer/trim_spice.py
index 9ddbe655..3518fac0 100644
--- a/compiler/characterizer/trim_spice.py
+++ b/compiler/characterizer/trim_spice.py
@@ -55,8 +55,8 @@ class trim_spice():
         else:
             col_address = 0
         # 1. Keep cells in the bitcell array based on WL and BL
-        wl_name = "wl[{}]".format(wl_address)
-        bl_name = "bl[{}]".format(int(self.words_per_row*data_bit + col_address))
+        wl_name = "wl_{}".format(wl_address)
+        bl_name = "bl_{}".format(int(self.words_per_row*data_bit + col_address))
 
         # Prepend info about the trimming
         addr_msg = "Keeping {} address".format(address)
@@ -75,8 +75,8 @@ class trim_spice():
         self.sp_buffer.insert(0, "* WARNING: This is a TRIMMED NETLIST.")
         
         
-        wl_regex = r"wl\d*\[{}\]".format(wl_address)
-        bl_regex = r"bl\d*\[{}\]".format(int(self.words_per_row*data_bit + col_address))
+        wl_regex = r"wl\d*_{}".format(wl_address)
+        bl_regex = r"bl\d*_{}".format(int(self.words_per_row*data_bit + col_address))
         self.remove_insts("bitcell_array",[wl_regex,bl_regex])
 
         # 2. Keep sense amps basd on BL
@@ -87,7 +87,7 @@ class trim_spice():
         self.remove_insts("column_mux_array",[bl_regex])
         
         # 4. Keep write driver based on DATA
-        data_regex = r"data\[{}\]".format(data_bit)
+        data_regex = r"data_{}".format(data_bit)
         self.remove_insts("write_driver_array",[data_regex])
 
         # 5. Keep wordline driver based on WL